Multi-Context in CGRAs

Multi-context support allows time-multiplexing the CGRA. In multi-context, multiple configuration bitstreams are loaded into a CGRA instead of just one. The CGRA cycles through the bitstreams according to a predefined pattern. Multi-context thus allows a small CGRA to realize a large application that could not otherwise “fit”, by trading off space for time.

A CGRA can support a certain number of contexts and can then operate at any II less than or equal to the II the architecture was generated for. Multi-context is implemented here using binary counters that drives multiplexer select inputs to select configuration bits based on the current context. Identical binary counters are located in each core CGRA tile: processing elements (PE), register file (RF), I/O, and memory port. Each of these counters is ceil(log2(II)) bits wide. The counters count in tandem: each counter in each core CGRA tile is outputting the same code in a given cycle. If II=4 and all contexts are used, then the counters count through the sequence: 00, 01, 10, 11, 00, … . The counters are also capable of working in a ``modulo’’ style if II<SII, where, if II, the counter would count through the sequence: 00, 01, 10, 00, … . An extra register is incorporated into the CGRA top module that indicates the number of used contexts (II). The output of this register is fed to one-hot counters throughout the CGRA fabric, so they cycle through only those one-hot codes consistent with the number of used contexts. The one-hot codes produced by counters drive AND/OR logic to select the configuration bit for the current context.

A verilog file named testbench.v is generated with the configuration bitstream for mapping the application onto the multi-context CGRA.

Generating Verilog

To generate verilog for the multi-context CGRA architecture, the initiation intervals (II) must be provided. The following command can be used to generate the verilog for multi-context CGRA:

$ "$CGRA_MAPPER" --II 4 -c adres --arch-opts "rows=2 cols=2" --gen-verilog .

The above command generated the CGRA verilog file with the filename cgrame.v

Generating Configuration Bitstream

To generate configuration bitstream for the multi-context CGRA architecture, the initiation interval (II) to be used needs to be provided as parameters. The II of the configuration bitstream must be less than or equal to the II of the generated verilog. The following command generates the configuration bitstream for multi-context CGRA:

$ "$CGRA_MAPPER" --II 3 -g graph_loop.dot -c adres --arch-opts "rows=2 cols=2" --gen-testbench .

A verilog file named testbench.v is generated with the configuration bitstream for mapping the application onto the multi-context CGRA.

ModelSim Simulation

For ModelSim simulation using the tool generated CGRA and configuration bitstream verilog files, a wrapper verilog file is also additionally required which instantiates both the CGRA verilog and configures it using the configuration bitstream verilog file (testbench.v). Examples of such wrapper verilog files can be found in the verilog-verif folder (verilog-verif/adres2x2-sum/multi-context/tb_src/tb_master.sv)