Coarse-grained reconfigurable architectures (CGRAs) are a style of programmable logic device situated between field-programmable gate arrays (FPGAs) and ASICs on the spectrums of programmability, performance and silicon-area cost. Unlike fine-grained FPGAs, CGRAs contain large coarse-grained logic blocks, having many inputs and outputs, and capable of performing complex ALU-like functions. Likewise, the programmable interconnect in CGRAs is datapath-like, where entire busses of signals are routed together in tandem, rather than individual logic signals. CGRAs are an up-and-coming promising platform for the realization of domain-specific compute accelerators.
CGRA-ME is an architectural modelling and exploration (ME) framework under active development at the Department of Electrical and Computer Engineering, University of Toronto. With CGRA-ME, an architect describes the CGRA they wish to model in an XML-based language. The XML-based model is parsed by CGRA-ME to form an in-memory representation of the CGRA device. Compute kernels (application benchmarks) can then be mapped onto the CGRA to assess its performance and area for a basket of applications drawn from a domain of interest.
CGRA-ME is open-source and freely downloadable for non-commercial research purposes.