This paper showcases CGRA-ME performing a study on different CGRA implementations - we synthesize both a standard-cell implementation as well as an FPGA-overlay implementation. CGRA-ME is used to model, map to, and create RTL for CGRA architectures with backend flows created for both types of physical design.

The paper will be presented in Session 2 on Wednesday March 26th at ISPD2018 in Seaside, California, USA.

Links to the presentation and paper will be posted shortly in the Publications section.