Floating Point Support

The Floating-Point ALUs in the ALU utilize FP cores generated by FloPoCo, an open-source FP core generator. FloPoCo allows the generation of FP cores in VHDL RTL based on specified input constraints, impacting factors such as the number of pipeline stages and customization for FPGA implementation with specific hard IP blocks. The FP cores adhere to the IEEE 754 single-precision standard (1-bit sign, 8-bit exponent, 23-bit mantissa) and can receive a new input every clock cycle (initiation interval (II)=1).

Since the FloPoCo ALUs do not follow the elastic protocol, CGRA-ME encapsulates the FP ALUs in an fp_wrapper. This wrapper incorporates valid/stop functionality on both the input and output sides of the ALU. Additionally, the wrapper temporarily halts the clock to the FP ALU when there is backpressure from buffOut. The wrapper is designed to be aware of the pipeline depth of the FP ALU, tracking data progress through the ALU using a shift register. It asserts valid to buffOut when an FP result is ready for storage.

The floating point processing elements support the following operations:

• Addition
• Multiplication
• Division
• Square Root