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| | RIKEN_PE_Elastic (std::string name, int pe_conn_in, int pe_conn_out, int II, int latency, Location Loc, int type, int buffer_depth=2, bool eb_enable=true, int contexts=1, bool pred=false, std::string pred_type="full") |
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| virtual std::string | GenericName () |
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| virtual | ~RIKEN_PE_Elastic () |
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| | Module (std::string name, Location, unsigned size=DEFAULT_SIZE, bool isElastic=false) |
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| | Module (std::string name, std::string template_name, Location loc={0, 0}, unsigned size=DEFAULT_SIZE, bool isElastic=false) |
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| virtual | ~Module () |
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| | Module (const Module &)=delete |
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| | Module (Module &&)=default |
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| Module & | operator= (const Module &)=delete |
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| Module & | operator= (Module &&)=default |
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| void | print () |
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| void | print_dot () |
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| void | print_ports () |
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| void | print_connections () |
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| void | print_submodules () |
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| void | print_configcells () |
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| void | addConfig (ConfigCell *c, std::vector< std::string > ConnectTo) |
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| void | addConfig (std::string name, std::vector< std::string > ConnectTo, int contexts, bool isElastic) |
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| void | addSubModule (Module *m) |
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| void | addSubModule (Module *m, double xPos, double yPos, double width, double height) |
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| void | connectPorts (std::string src, std::string dst, bool isElastic) |
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| void | addConnection (std::string src, std::string dst, bool isInMRRG=true) |
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| void | addElasticConnection (std::string src, std::string dst) |
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| void | addPort (std::string portname, port_type pt, unsigned size) |
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| void | addPort (std::string portname, port_type pt, unsigned size, bool isElastic) |
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| void | addElasticPort (std::string portname, port_type pt, unsigned size) |
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| void | addPort (std::string portname, port_type pt, std::string ParameterName, unsigned size) |
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| void | addPort (std::string portname, port_type pt, std::string ParameterName, unsigned size, bool isElastic) |
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| void | addElasticPort (std::string portname, port_type pt, std::string ParameterName, unsigned size) |
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| void | addParameter (std::string parameterName, unsigned parameterValue) |
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| void | addVerilogPort (std::string name, port_type pt, std::string parameter, unsigned size) |
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| void | genConfigOrder (std::vector< ConfigCell * > &ConfigTable) const |
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| Module * | getSubModule (std::string) |
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| bool | isSubModule (Module *) |
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| Module * | getModule (std::string, std::string err_context="") |
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| Module * | getModuleFromPortName (std::string full_port_name, std::string err_context="") |
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| Port * | getPort (std::string full_port_name, std::string err_context="") |
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| int | getSize () const |
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| auto & | getName () const |
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| std::string | ReturnPath () const |
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| bool | hasConfigCells () const |
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| virtual BitConfig | getBitConfig (const MRRG &mrrg, const OpGraph &og, const Mapping &map, const ConfigCell &ccell, const MRRGNodesFromOpNode &mrrg_nodes_from_op_node, const MRRGNodesFromValNode &mrrg_nodes_from_val_node) const |
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| virtual MRRG * | createMRRG (unsigned contexts) |
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| void | genVerilogCGRAME (std::string dir) |
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| void | genVerilogCoreIR (std::string dir, int contexts) |
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| void | GetModulesToPrint (std::queue< Module * > &ToPrint, std::set< std::string > &PrintedModMap) |
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| virtual void | GenModuleVerilog () |
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| CoreIR::TypeGenFun | makeCoreIRInterfaceGenerator () |
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| CoreIR::ModuleDefGenFun | makeCoreIRModuleDefinitonGenerator () |
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| virtual void | CoreIRGenModuleVerilog (CoreIR::Context *c, int contexts) |
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| bool | setNodePosition (const std::string &nodeName, double x, double y) |
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| std::pair< bool, std::pair< double, double > > | getSubModulePosition (const std::string &submodName) |
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| std::pair< bool, std::pair< double, double > > | getNodePosition (const std::string &nodeName) |
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| bool | addsSynchronousCircuitry () const |
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Definition at line 30 of file UserModules.h.