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CGRA-ME
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#include <CGRA/BitSetting.h>#include <CGRA/Exception.h>#include <CGRA/MRRG.h>#include <CGRA/Mapping.h>#include <CGRA/OpGraph.h>#include <coreir/ir/fwd_declare.h>#include <unordered_map>#include <queue>#include <vector>#include <map>#include <set>#include <string>#include <iosfwd>Go to the source code of this file.
Classes | |
| struct | Port |
| struct | Connection |
| class | PrintList |
| struct | ResolvedVeroligModuleParameter |
| struct | Location |
| class | Module |
| struct | Module::VisualPositionRect |
| struct | Module::VisualPositionPoint |
| struct | PipelineMode |
| struct | LLVMMode |
| class | FuncUnit |
| Functional Unit, does one of a set of arithmetic computations. More... | |
| class | FracUnit |
| class | FracMulUnit |
| class | FracAddUnit |
| class | MemoryUnit |
| Single load & store memory operations. More... | |
| class | ConstUnit |
| class | Register |
| A simple latency element with an enable signal; a data flip-flop. More... | |
| class | Multiplexer |
| Zero-cycle latency multiplexer. More... | |
| class | TruncateInput |
| Zero-cycle latency split input. More... | |
| class | SelMultiplexer |
| 2 Zero-cycle latency multiplexers for predication support. More... | |
| class | DeMux |
| Zero-cycle latency DeMultiplexer. More... | |
| class | RegisterFile |
| Multiplexed registers. More... | |
| class | Crossbar |
| class | TriState |
| class | IO |
| Supports the input and output ops. Will add an external port at the top-level of generated verilog. More... | |
| class | DisconnectedSource |
| For when an input is unused, but a connection is required anyway. More... | |
| class | DisconnectedSink |
| For when an output is unused, but a connection is required anyway. More... | |
| class | CustomModule |
| class | CustomModuleSingleInput |
| class | UserModule |
| class | ConfigCell |
| class | EventTransitionTable |
| class | ContextCell |
| class | ContextCounter |
| class | CaseStatement |
| class | Compare |
Macros | |
| #define | MOD_II(x) ((x) % II) |
Typedefs | |
| using | StringMatrix = std::vector< std::vector< std::string > > |
| using | MRRGNodesFromOpNode = std::map< OpGraphOp *, std::set< MRRG::NodeDescriptor > > |
| using | MRRGNodesFromValNode = std::map< OpGraphVal *, std::set< MRRG::NodeDescriptor > > |
Enumerations | |
| enum | port_type { PORT_INPUT, PORT_OUTPUT, PORT_OUTPUT_REG, PORT_BIDIR, PORT_CONFIG, PORT_UNSPECIFIED } |
| enum | CGRABlockType { STANDARD_NOBYPASS, STANDARD_BYPASS, STANDARD_DIAGONAL } |
| enum | VerilogType { VerilogType::CGRAME = 0, VerilogType::CoreIR = 1 } |
Functions | |
| std::istream & | operator>> (std::istream &is, port_type &porttype) |
| std::istream & | operator>> (std::istream &is, CGRABlockType &blocktype) |
| std::ostream & | operator<< (std::ostream &os, VerilogType vt) |
Variables | |
| const char *const | SET_INDENT = " " |
| const char *const | SET_DOUBLE_INDENT = " " |
| const char *const | SET_TRIPLE_INDENT = " " |
| const char *const | SET_QUAD_INDENT = " " |
| const char *const | SET_PENTA_INDENT = " " |
| const char *const | SET_HEXA_INDENT = " " |
| const char *const | PORT_DEFAULT_CONNECTION = "/* A PORT IS UNCONNECTED */" |
| const bool | MODULE_DEBUG_PRINTING = false |
| const int | DEFAULT_SIZE = 32 |
| const int | PARAMETERIZED = 0 |
| using MRRGNodesFromOpNode = std::map<OpGraphOp*, std::set<MRRG::NodeDescriptor> > |
| using MRRGNodesFromValNode = std::map<OpGraphVal*, std::set<MRRG::NodeDescriptor> > |
| using StringMatrix = std::vector<std::vector<std::string> > |
| enum CGRABlockType |
| enum port_type |
|
strong |
| std::ostream& operator<< | ( | std::ostream & | os, |
| VerilogType | vt | ||
| ) |
Definition at line 98 of file Module.cpp.
| std::istream& operator>> | ( | std::istream & | is, |
| CGRABlockType & | blocktype | ||
| ) |
Definition at line 166 of file ModuleComposites.cpp.
| std::istream& operator>> | ( | std::istream & | is, |
| port_type & | porttype | ||
| ) |
Definition at line 2381 of file Module.cpp.
| const char* const PORT_DEFAULT_CONNECTION = "/* A PORT IS UNCONNECTED */" |
1.8.17