Functional Unit, does one of a set of arithmetic computations. More...

#include <Module.h>

Inheritance diagram for FuncUnit:

Public Member Functions
	FuncUnit (std::string name, Location, std::vector< OpGraphOpCode > supported_modes, unsigned size, int II, int latency, bool isElastic=false)

virtual	~FuncUnit ()

virtual MRRG *	createMRRG (unsigned II) override

virtual BitConfig	getBitConfig (const MRRG &mrrg, const OpGraph &og, const Mapping &map, const ConfigCell &ccell, const MRRGNodesFromOpNode &mrrg_nodes_from_op_node, const MRRGNodesFromValNode &mrrg_nodes_from_val_node) const override

virtual std::string	GenericName () override

int	getII () const

int	getLatency () const

auto &	getSupportedModes () const

Public Member Functions inherited from Module
	Module (std::string name, Location, unsigned size=DEFAULT_SIZE, bool isElastic=false)

	Module (std::string name, std::string template_name, Location loc={0, 0}, unsigned size=DEFAULT_SIZE, bool isElastic=false)

virtual	~Module ()

	Module (const Module &)=delete

	Module (Module &&)=default

Module &	operator= (const Module &)=delete

Module &	operator= (Module &&)=default

void	print ()

void	print_dot ()

void	print_ports ()

void	print_connections ()

void	print_submodules ()

void	print_configcells ()

void	addConfig (ConfigCell *c, std::vector< std::string > ConnectTo)

void	addConfig (std::string name, std::vector< std::string > ConnectTo, int contexts, bool isElastic)

void	addSubModule (Module *m)

void	addSubModule (Module *m, double xPos, double yPos, double width, double height)

void	connectPorts (std::string src, std::string dst, bool isElastic)

void	addConnection (std::string src, std::string dst, bool isInMRRG=true)

void	addElasticConnection (std::string src, std::string dst)

void	addPort (std::string portname, port_type pt, unsigned size)

void	addPort (std::string portname, port_type pt, unsigned size, bool isElastic)

void	addElasticPort (std::string portname, port_type pt, unsigned size)

void	addPort (std::string portname, port_type pt, std::string ParameterName, unsigned size)

void	addPort (std::string portname, port_type pt, std::string ParameterName, unsigned size, bool isElastic)

void	addElasticPort (std::string portname, port_type pt, std::string ParameterName, unsigned size)

void	addParameter (std::string parameterName, unsigned parameterValue)

void	addVerilogPort (std::string name, port_type pt, std::string parameter, unsigned size)

void	genConfigOrder (std::vector< ConfigCell * > &ConfigTable) const

Module *	getSubModule (std::string)

bool	isSubModule (Module *)

Module *	getModule (std::string, std::string err_context="")

Module *	getModuleFromPortName (std::string full_port_name, std::string err_context="")

Port *	getPort (std::string full_port_name, std::string err_context="")

int	getSize () const

auto &	getName () const

std::string	ReturnPath () const

bool	hasConfigCells () const

void	genVerilogCGRAME (std::string dir)

void	genVerilogCoreIR (std::string dir, int contexts)

void	GetModulesToPrint (std::queue< Module * > &ToPrint, std::set< std::string > &PrintedModMap)

virtual void	GenModuleVerilog ()

CoreIR::TypeGenFun	makeCoreIRInterfaceGenerator ()

CoreIR::ModuleDefGenFun	makeCoreIRModuleDefinitonGenerator ()

virtual void	CoreIRGenModuleVerilog (CoreIR::Context *c, int contexts)

bool	setNodePosition (const std::string &nodeName, double x, double y)

std::pair< bool, std::pair< double, double > >	getSubModulePosition (const std::string &submodName)

std::pair< bool, std::pair< double, double > >	getNodePosition (const std::string &nodeName)

bool	addsSynchronousCircuitry () const

Static Public Attributes
static const std::map< OpGraphOpCode, LLVMMode >	all_modes

Protected Attributes
PipelineMode	pipeline_mode

std::vector< OpGraphOpCode >	supported_modes

Protected Attributes inherited from Module
unsigned	data_size

std::string	templateName

std::string	name

std::map< std::string, VisualPositionRect >	submodule_relative_position = {}

std::map< std::string, VisualPositionPoint >	node_relative_position = {}

bool	adds_synchronous_circuitry

Additional Inherited Members
Public Attributes inherited from Module
std::map< std::string, unsigned >	parameterlist

std::map< std::string, Port * >	ports

std::map< Port , Connection >	connections

std::map< std::string, Module * >	submodules

std::map< std::string, ConfigCell * >	configcells

std::vector< Port >	portsToPropagate

double	area = 0.

unsigned int	hierarchyLevel = 0

bool	isLastInHierarchy

bool	isElastic = false

bool	submodsSet

Location	loc

int	overridenFanoutCount = -1

Module *	parent = nullptr

Protected Member Functions inherited from Module
void	GetConfigsToPrint (std::queue< ConfigCell * > &q, std::set< unsigned > &uniq)

void	GenModuleHeader (bool HasConfig, bool HasRegisters)

void	GenParameters ()

void	GenPortSpecs (bool HasConfig, bool HasRegisters)

virtual void	GenConnections ()

virtual void	GenFunctionality ()

void	CoreIRGetModulesToPrint (std::queue< Module * > &ToPrint, std::set< std::string > &PrintedModMap)

virtual nlohmann::json	CoreIRGenFunctionality ()

void	GenerateMatrix (StringMatrix &Matrix)

void	DetermineConnections (StringMatrix &Matrix, PrintList &WireList, PrintList &SubmodList, PrintList &AssignList)

virtual std::vector< ResolvedVeroligModuleParameter >	ResolveVerilogParameters () const

int	FindPortIndex (std::string PortName)

int	FindSubmoduleIndex (std::string SubmoduleName)

Detailed Description

Functional Unit, does one of a set of arithmetic computations.

Ports:

'in_a' is an input
'in_b' is an input
'out' is an output
'select' is the configuration port. Only present if more than one supported_modes .

Definition at line 406 of file Module.h.

Constructor & Destructor Documentation

◆ FuncUnit()

FuncUnit::FuncUnit	(	std::string	name,
		Location	loc,
		std::vector< OpGraphOpCode >	supported_modes,
		unsigned	size,
		int	II,
		int	latency,
		bool	isElastic = `false`
	)

Definition at line 53 of file ModuleFuncUnit.cpp.

◆ ~FuncUnit()

FuncUnit::~FuncUnit ( )

virtual

Definition at line 191 of file ModuleFuncUnit.cpp.

Member Function Documentation

◆ createMRRG()

MRRG * FuncUnit::createMRRG ( unsigned II = 1 )

overridevirtual

Reimplemented from Module.

Definition at line 195 of file ModuleFuncUnit.cpp.

◆ GenericName()

std::string FuncUnit::GenericName ( )

overridevirtual

Reimplemented from Module.

Definition at line 40 of file ModuleFuncUnit.cpp.

◆ getBitConfig()

BitConfig FuncUnit::getBitConfig	(	const MRRG &	mrrg,
		const OpGraph &	og,
		const Mapping &	map,
		const ConfigCell &	ccell,
		const MRRGNodesFromOpNode &	mrrg_nodes_from_op_node,
		const MRRGNodesFromValNode &	mrrg_nodes_from_val_node
	)		const

overridevirtual

Reimplemented from Module.

Definition at line 146 of file ModuleFuncUnit.cpp.

◆ getII()

int FuncUnit::getII ( ) const

inline

Definition at line 428 of file Module.h.

◆ getLatency()

int FuncUnit::getLatency ( ) const

inline

Definition at line 429 of file Module.h.

◆ getSupportedModes()

auto& FuncUnit::getSupportedModes ( ) const

inline

Definition at line 430 of file Module.h.

Member Data Documentation

◆ all_modes

const std::map< OpGraphOpCode, LLVMMode > FuncUnit::all_modes

static

Initial value:

=
{
    
    
    
    {OpCode::NOP,    {"op_nop",      "nop",          {"assign c = a;"},           "nop_sel"}},
    {OpCode::ADD,    {"op_add",      "add",         {"assign c = a + b ;"},      "add_sel"}},
    {OpCode::SUB,    {"op_sub",      "sub",         {"assign c = a - b;"},      "sub_sel"}},
    {OpCode::MUL,    {"op_multiply", "multiply",    {"assign c = a * b;"},      "mul_sel"}},
    {OpCode::DIV,    {"op_divide",   "divide",      {"assign c = a / b;"},      "div_sel"}},
    {OpCode::AND,    {"op_and",      "and",         {"assign c = a & b;"},      "and_sel"}},
    {OpCode::OR,     {"op_or",       "or",          {"assign c = a | b;"},      "or_sel"}},
    {OpCode::XOR,    {"op_xor",      "xor",         {"assign c = a ^ b;"},      "xor_sel"}},
    {OpCode::SHL,    {"op_shl",      "shl",         {"assign c = a << b;"},     "shl_sel"}},
    {OpCode::LSHR,   {"op_lshr",     "lshr",        {"assign c = a >> b;"},     "lshr_sel"}},
    {OpCode::ASHR,   {"op_ashr",     "ashr",        {"assign c = a >>> b;"},    "ashr_sel"}},
    {OpCode::CONST,  {"op_const",    "const",       {"//const;"},               "const_sel"}},
    {OpCode::LOAD,   {"op_load",     "load",        {"//load;"},                "load_sel"}},
    {OpCode::STORE,  {"op_store",    "store",       {"//store;"},               "store_sel"}},
    {OpCode::ICMP,   {"op_cmp",      "cmp",     {"assign c = a == b? 1: 0;"},"cmp_sel"}}
}

Definition at line 432 of file Module.h.

◆ pipeline_mode

PipelineMode FuncUnit::pipeline_mode

protected

Definition at line 434 of file Module.h.

◆ supported_modes

std::vector<OpGraphOpCode> FuncUnit::supported_modes

protected

Definition at line 435 of file Module.h.

The documentation for this class was generated from the following files:

/media/maple_tb_disk/wicklun2/cgra-me-website/cgra-me/inc/CGRA/Module.h
/media/maple_tb_disk/wicklun2/cgra-me-website/cgra-me/src/core/ModuleFuncUnit.cpp

Public Member Functions

Static Public Attributes

Protected Attributes

Additional Inherited Members

Detailed Description

Constructor & Destructor Documentation

◆ FuncUnit()

◆ ~FuncUnit()

Member Function Documentation

◆ createMRRG()

◆ GenericName()

◆ getBitConfig()

◆ getII()

◆ getLatency()

◆ getSupportedModes()

Member Data Documentation

◆ all_modes

◆ pipeline_mode

◆ supported_modes