CGRA-ME
Public Member Functions | List of all members
FPAdd Class Reference

#include <ModuleFPUnit.h>

Inheritance diagram for FPAdd:
Module

Public Member Functions

 FPAdd (std::string name, Location, unsigned size)
 
virtual ~FPAdd ()
 
virtual std::string GenericName () override
 
virtual nlohmann::json CoreIRGenFunctionality () override
 
- Public Member Functions inherited from Module
 Module (std::string name, Location, unsigned size=DEFAULT_SIZE, bool isElastic=false)
 
 Module (std::string name, std::string template_name, Location loc={0, 0}, unsigned size=DEFAULT_SIZE, bool isElastic=false)
 
virtual ~Module ()
 
 Module (const Module &)=delete
 
 Module (Module &&)=default
 
Module & operator= (const Module &)=delete
 
Module & operator= (Module &&)=default
 
void print ()
 
void print_dot ()
 
void print_ports ()
 
void print_connections ()
 
void print_submodules ()
 
void print_configcells ()
 
void addConfig (ConfigCell *c, std::vector< std::string > ConnectTo)
 
void addConfig (std::string name, std::vector< std::string > ConnectTo, int contexts, bool isElastic)
 
void addSubModule (Module *m)
 
void addSubModule (Module *m, double xPos, double yPos, double width, double height)
 
void connectPorts (std::string src, std::string dst, bool isElastic)
 
void addConnection (std::string src, std::string dst, bool isInMRRG=true)
 
void addElasticConnection (std::string src, std::string dst)
 
void addPort (std::string portname, port_type pt, unsigned size)
 
void addPort (std::string portname, port_type pt, unsigned size, bool isElastic)
 
void addElasticPort (std::string portname, port_type pt, unsigned size)
 
void addPort (std::string portname, port_type pt, std::string ParameterName, unsigned size)
 
void addPort (std::string portname, port_type pt, std::string ParameterName, unsigned size, bool isElastic)
 
void addElasticPort (std::string portname, port_type pt, std::string ParameterName, unsigned size)
 
void addParameter (std::string parameterName, unsigned parameterValue)
 
void addVerilogPort (std::string name, port_type pt, std::string parameter, unsigned size)
 
void genConfigOrder (std::vector< ConfigCell * > &ConfigTable) const
 
Module * getSubModule (std::string)
 
bool isSubModule (Module *)
 
Module * getModule (std::string, std::string err_context="")
 
Module * getModuleFromPortName (std::string full_port_name, std::string err_context="")
 
Port * getPort (std::string full_port_name, std::string err_context="")
 
int getSize () const
 
auto & getName () const
 
std::string ReturnPath () const
 
bool hasConfigCells () const
 
virtual BitConfig getBitConfig (const MRRG &mrrg, const OpGraph &og, const Mapping &map, const ConfigCell &ccell, const MRRGNodesFromOpNode &mrrg_nodes_from_op_node, const MRRGNodesFromValNode &mrrg_nodes_from_val_node) const
 
virtual MRRG * createMRRG (unsigned contexts)
 
void genVerilogCGRAME (std::string dir)
 
void genVerilogCoreIR (std::string dir, int contexts)
 
void GetModulesToPrint (std::queue< Module * > &ToPrint, std::set< std::string > &PrintedModMap)
 
virtual void GenModuleVerilog ()
 
CoreIR::TypeGenFun makeCoreIRInterfaceGenerator ()
 
CoreIR::ModuleDefGenFun makeCoreIRModuleDefinitonGenerator ()
 
virtual void CoreIRGenModuleVerilog (CoreIR::Context *c, int contexts)
 
bool setNodePosition (const std::string &nodeName, double x, double y)
 
std::pair< bool, std::pair< double, double > > getSubModulePosition (const std::string &submodName)
 
std::pair< bool, std::pair< double, double > > getNodePosition (const std::string &nodeName)
 
bool addsSynchronousCircuitry () const
 

Additional Inherited Members

- Public Attributes inherited from Module
std::map< std::string, unsigned > parameterlist
 
std::map< std::string, Port * > ports
 
std::map< Port *, Connection * > connections
 
std::map< std::string, Module * > submodules
 
std::map< std::string, ConfigCell * > configcells
 
std::vector< Port > portsToPropagate
 
double area = 0.
 
unsigned int hierarchyLevel = 0
 
bool isLastInHierarchy
 
bool isElastic = false
 
bool submodsSet
 
Location loc
 
int overridenFanoutCount = -1
 
Module * parent = nullptr
 
- Protected Member Functions inherited from Module
void GetConfigsToPrint (std::queue< ConfigCell * > &q, std::set< unsigned > &uniq)
 
void GenModuleHeader (bool HasConfig, bool HasRegisters)
 
void GenParameters ()
 
void GenPortSpecs (bool HasConfig, bool HasRegisters)
 
virtual void GenConnections ()
 
virtual void GenFunctionality ()
 
void CoreIRGetModulesToPrint (std::queue< Module * > &ToPrint, std::set< std::string > &PrintedModMap)
 
void GenerateMatrix (StringMatrix &Matrix)
 
void DetermineConnections (StringMatrix &Matrix, PrintList &WireList, PrintList &SubmodList, PrintList &AssignList)
 
virtual std::vector< ResolvedVeroligModuleParameter > ResolveVerilogParameters () const
 
int FindPortIndex (std::string PortName)
 
int FindSubmoduleIndex (std::string SubmoduleName)
 
- Protected Attributes inherited from Module
unsigned data_size
 
std::string templateName
 
std::string name
 
std::map< std::string, VisualPositionRect > submodule_relative_position = {}
 
std::map< std::string, VisualPositionPoint > node_relative_position = {}
 
bool adds_synchronous_circuitry
 

Detailed Description

Definition at line 6 of file ModuleFPUnit.h.

Constructor & Destructor Documentation

◆ FPAdd()

FPAdd::FPAdd ( std::string  name,
Location  loc,
unsigned  size 
)

Definition at line 6 of file ModuleFPUnit.cpp.

◆ ~FPAdd()

FPAdd::~FPAdd ( )
virtual

Definition at line 106 of file ModuleFPUnit.cpp.

Member Function Documentation

◆ CoreIRGenFunctionality()

nlohmann::json FPAdd::CoreIRGenFunctionality ( )
overridevirtual

Reimplemented from Module.

Definition at line 27 of file ModuleFPUnit.cpp.

◆ GenericName()

std::string FPAdd::GenericName ( )
overridevirtual

Reimplemented from Module.

Definition at line 21 of file ModuleFPUnit.cpp.

The documentation for this class was generated from the following files:
Generated on Fri Nov 17 2023 12:26:52 for CGRA-ME by   doxygen 1.8.17