CGRA-ME
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#include <CGRA.h>
Public Types | |
using | BitArray = std::vector< std::vector< BitSetting > > |
Public Member Functions | |
void | append (const ConfigCell *ccell, const BitArray &bits, int con_used=0) |
void | printTestbench (std::ostream &os, const int &II, bool is_elastic=false) const |
const BitArray & | settingFor (const ConfigCell *cc) const |
auto & | ccellOrder () const |
Private Attributes | |
std::unordered_map< const ConfigCell *, BitArray > | setting_storage = {} |
std::vector< const ConfigCell * > | ccell_order = {} |
std::unordered_map< const ConfigCell *, int > | contexts_used = {} |
Friends | |
std::ostream & | operator<< (std::ostream &os, const BitStream &bs) |
Represents a configuration bitstream. Provides storage for BitSettings, and an order among ConfigCells
using BitStream::BitArray = std::vector<std::vector<BitSetting> > |
void BitStream::append | ( | const ConfigCell * | ccell, |
const BitArray & | bits, | ||
int | con_used = 0 |
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) |
Add the given bits to the configuration database, and place ccell at the end of the ConfigCell order.
Definition at line 19 of file BitStream.cpp.
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inline |
void BitStream::printTestbench | ( | std::ostream & | os, |
const int & | II, | ||
bool | is_elastic = false |
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) | const |
Prints out a Verilog file intended to help with creating a testbench for the CGRA.
Bitstream is given all the bits for an element at once. Bits are given in order from last cycle to first cycle. From last bit to first bit.
Definition at line 44 of file BitStream.cpp.
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inline |
Get the configuration for a particular ConfigCell throws if it does not exist.
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friend |
Print the bitstream in a human-friendly way.
Prints out the bit settings for each element. For each element, the bit setting is printed from cycle 0 to II, from first bit to last bit
Definition at line 28 of file BitStream.cpp.
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private |
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private |
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private |