#include <CGRA/Module.h>
#include <CGRA/ModuleProcedures.h>
#include <CGRA/ModuleElastic.h>
#include <coreir/passes/analysis/coreirjson.h>
#include <ios>
#include <fstream>
#include <ostream>
#include <sstream>
#include <regex>

Functions
std::ostream &	operator<< (std::ostream &os, VerilogType vt)

static bool	getmoduleport (std::string name, std::string module, std::string port)

std::istream &	operator>> (std::istream &is, port_type &type)

Variables
static const std::map< std::string, port_type >	port_type_map

Function Documentation

◆ getmoduleport()

static bool getmoduleport	(	std::string	name,
		std::string *	module,
		std::string *	port
	)

static

Definition at line 1065 of file Module.cpp.

◆ operator<<()

std::ostream& operator<<	(	std::ostream &	os,
		VerilogType	vt
	)

Definition at line 98 of file Module.cpp.

◆ operator>>()

std::istream& operator>>	(	std::istream &	is,
		port_type &	type
	)

Definition at line 2381 of file Module.cpp.

Variable Documentation

◆ port_type_map

const std::map<std::string, port_type> port_type_map

static

Initial value:

=
{
    {"input", PORT_INPUT},
    {"output", PORT_OUTPUT},
    {"output-reg", PORT_OUTPUT_REG},
    {"bidir", PORT_BIDIR},
    {"unspecified", PORT_UNSPECIFIED},
}

Definition at line 2372 of file Module.cpp.