Coarse-grained reconfigurable architectures (CGRAs) are programmable hardware devices situated between field-programmable gate arrays (FPGAs) and ASICs on the spectrum of programmability. Unlike fine-grained FPGAs, CGRAs contain large coarse-grained logic blocks, having many inputs and outputs, and capable of performing complex ALU-like functions. Likewise, the programmable interconnect in CGRAs is datapath-like, where entire busses of signals are routed together in tandem, rather than individual logic signals. CGRAs are an up-and-coming promising platform for the realization of domain-specific computing accelerators.

CGRA-ME is an architectural modelling and exploration (ME) framework under active development at the Department of Electrical and Computer Engineering, University of Toronto. With CGRA-ME, an architect describes the CGRA they wish to model in an XML-based language. The XML-based model is parsed by CGRA-ME to form an in-memory representation of the CGRA device. Compute kernels (application benchmarks) can then be mapped onto the CGRA to assess its performance and area for a basket of applications drawn from a domain of interest. The framework also provides automatic generation of Verilog RTL for the modeled architecture. This allows the architect to simulate for verication purposes, and perform synthesis to either an ASIC or FPGA-overlay implementation of the CGRA, assessing speed, area, and power consumption.

CGRA-ME is open-source and freely downloadable for non-commercial research purposes.

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