At DAC2018 in San Francisco, California, we will present our work on an integer linear programming formulation for mapping applications to CGRAs. This ILP-based mapper is built into our framework and is included in the current release.
Links to the presentation and paper will be posted in the Publications section.
This paper showcases CGRA-ME performing a study on different CGRA implementations - we synthesize both a standard-cell implementation as well as an FPGA-overlay implementation. CGRA-ME is used to model, map to, and create RTL for CGRA architectures with backend flows created for both types of physical design.
The paper will be presented in Session 2 on Wednesday March 26th at ISPD2018 in Seaside, California, USA.
Links to the presentation and paper will be posted shortly in the Publications section.
We are glad to announce that the first publication on the CGRA-ME framework has been accepted to ASAP2017!
The paper will be presented in Paper Session 7 on Wednesday July 12th at ASAP2017 in Seattle, Washington, USA.
Links to the presentation and paper is posted in the Publications section.
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