Zero-cycle latency multiplexer. More...

#include <Module.h>

Inheritance diagram for Multiplexer:

Public Member Functions
	Multiplexer (std::string, Location, unsigned mux_size, unsigned size=DEFAULT_SIZE, bool isElastic=false)

virtual	~Multiplexer ()

virtual std::string	GenericName () override

virtual void	GenFunctionality () override

virtual nlohmann::json	CoreIRGenFunctionality () override

virtual BitConfig	getBitConfig (const MRRG &mrrg, const OpGraph &og, const Mapping &map, const ConfigCell &ccell, const MRRGNodesFromOpNode &mrrg_nodes_from_op_node, const MRRGNodesFromValNode &mrrg_nodes_from_val_node) const override

int	getMuxSize ()

MRRG *	createMRRG (unsigned II) override

Public Member Functions inherited from Module
	Module (std::string name, Location, unsigned size=DEFAULT_SIZE, bool isElastic=false)

	Module (std::string name, std::string template_name, Location loc={0, 0}, unsigned size=DEFAULT_SIZE, bool isElastic=false)

virtual	~Module ()

	Module (const Module &)=delete

	Module (Module &&)=default

Module &	operator= (const Module &)=delete

Module &	operator= (Module &&)=default

void	print ()

void	print_dot ()

void	print_ports ()

void	print_connections ()

void	print_submodules ()

void	print_configcells ()

void	addConfig (ConfigCell *c, std::vector< std::string > ConnectTo)

void	addConfig (std::string name, std::vector< std::string > ConnectTo, int contexts, bool isElastic)

void	addSubModule (Module *m)

void	addSubModule (Module *m, double xPos, double yPos, double width, double height)

void	connectPorts (std::string src, std::string dst, bool isElastic)

void	addConnection (std::string src, std::string dst, bool isInMRRG=true)

void	addElasticConnection (std::string src, std::string dst)

void	addPort (std::string portname, port_type pt, unsigned size)

void	addPort (std::string portname, port_type pt, unsigned size, bool isElastic)

void	addElasticPort (std::string portname, port_type pt, unsigned size)

void	addPort (std::string portname, port_type pt, std::string ParameterName, unsigned size)

void	addPort (std::string portname, port_type pt, std::string ParameterName, unsigned size, bool isElastic)

void	addElasticPort (std::string portname, port_type pt, std::string ParameterName, unsigned size)

void	addParameter (std::string parameterName, unsigned parameterValue)

void	addVerilogPort (std::string name, port_type pt, std::string parameter, unsigned size)

void	genConfigOrder (std::vector< ConfigCell * > &ConfigTable) const

Module *	getSubModule (std::string)

bool	isSubModule (Module *)

Module *	getModule (std::string, std::string err_context="")

Module *	getModuleFromPortName (std::string full_port_name, std::string err_context="")

Port *	getPort (std::string full_port_name, std::string err_context="")

int	getSize () const

auto &	getName () const

std::string	ReturnPath () const

bool	hasConfigCells () const

void	genVerilogCGRAME (std::string dir)

void	genVerilogCoreIR (std::string dir, int contexts)

void	GetModulesToPrint (std::queue< Module * > &ToPrint, std::set< std::string > &PrintedModMap)

virtual void	GenModuleVerilog ()

CoreIR::TypeGenFun	makeCoreIRInterfaceGenerator ()

CoreIR::ModuleDefGenFun	makeCoreIRModuleDefinitonGenerator ()

virtual void	CoreIRGenModuleVerilog (CoreIR::Context *c, int contexts)

bool	setNodePosition (const std::string &nodeName, double x, double y)

std::pair< bool, std::pair< double, double > >	getSubModulePosition (const std::string &submodName)

std::pair< bool, std::pair< double, double > >	getNodePosition (const std::string &nodeName)

bool	addsSynchronousCircuitry () const

Private Attributes
int	mux_size

Additional Inherited Members
Public Attributes inherited from Module
std::map< std::string, unsigned >	parameterlist

std::map< std::string, Port * >	ports

std::map< Port , Connection >	connections

std::map< std::string, Module * >	submodules

std::map< std::string, ConfigCell * >	configcells

std::vector< Port >	portsToPropagate

double	area = 0.

unsigned int	hierarchyLevel = 0

bool	isLastInHierarchy

bool	isElastic = false

bool	submodsSet

Location	loc

int	overridenFanoutCount = -1

Module *	parent = nullptr

Protected Member Functions inherited from Module
void	GetConfigsToPrint (std::queue< ConfigCell * > &q, std::set< unsigned > &uniq)

void	GenModuleHeader (bool HasConfig, bool HasRegisters)

void	GenParameters ()

void	GenPortSpecs (bool HasConfig, bool HasRegisters)

virtual void	GenConnections ()

void	CoreIRGetModulesToPrint (std::queue< Module * > &ToPrint, std::set< std::string > &PrintedModMap)

void	GenerateMatrix (StringMatrix &Matrix)

void	DetermineConnections (StringMatrix &Matrix, PrintList &WireList, PrintList &SubmodList, PrintList &AssignList)

virtual std::vector< ResolvedVeroligModuleParameter >	ResolveVerilogParameters () const

int	FindPortIndex (std::string PortName)

int	FindSubmoduleIndex (std::string SubmoduleName)

Protected Attributes inherited from Module
unsigned	data_size

std::string	templateName

std::string	name

std::map< std::string, VisualPositionRect >	submodule_relative_position = {}

std::map< std::string, VisualPositionPoint >	node_relative_position = {}

bool	adds_synchronous_circuitry

Detailed Description

Zero-cycle latency multiplexer.

Ports:

'inN' where N is replaced by the number of the input port you are refering to (counting starts at 0)
'out' is the output of the mux
'select' decides which input to take

Definition at line 592 of file Module.h.

Constructor & Destructor Documentation

◆ Multiplexer()

Multiplexer::Multiplexer	(	std::string	name,
		Location	loc,
		unsigned	mux_size,
		unsigned	size = `DEFAULT_SIZE`,
		bool	isElastic = `false`
	)

Definition at line 472 of file ModuleRoutingStructures.cpp.

◆ ~Multiplexer()

Multiplexer::~Multiplexer ( )

virtual

Definition at line 706 of file ModuleRoutingStructures.cpp.

Member Function Documentation

◆ CoreIRGenFunctionality()

nlohmann::json Multiplexer::CoreIRGenFunctionality ( )

overridevirtual

Reimplemented from Module.

Definition at line 515 of file ModuleRoutingStructures.cpp.

◆ createMRRG()

MRRG * Multiplexer::createMRRG ( unsigned II = 1 )

overridevirtual

Reimplemented from Module.

Definition at line 682 of file ModuleRoutingStructures.cpp.

◆ GenericName()

std::string Multiplexer::GenericName ( )

overridevirtual

Reimplemented from Module.

Definition at line 497 of file ModuleRoutingStructures.cpp.

◆ GenFunctionality()

void Multiplexer::GenFunctionality ( )

overridevirtual

Reimplemented from Module.

Definition at line 504 of file ModuleRoutingStructures.cpp.

◆ getBitConfig()

BitConfig Multiplexer::getBitConfig	(	const MRRG &	mrrg,
		const OpGraph &	og,
		const Mapping &	map,
		const ConfigCell &	ccell,
		const MRRGNodesFromOpNode &	mrrg_nodes_from_op_node,
		const MRRGNodesFromValNode &	mrrg_nodes_from_val_node
	)		const

overridevirtual

Reimplemented from Module.

Definition at line 609 of file ModuleRoutingStructures.cpp.

◆ getMuxSize()

int Multiplexer::getMuxSize ( )

inline

Definition at line 607 of file Module.h.

Member Data Documentation

◆ mux_size

int Multiplexer::mux_size

private

Definition at line 610 of file Module.h.

The documentation for this class was generated from the following files:

/media/maple_tb_disk/wicklun2/cgra-me-website/cgra-me/inc/CGRA/Module.h
/media/maple_tb_disk/wicklun2/cgra-me-website/cgra-me/src/core/ModuleRoutingStructures.cpp

Public Member Functions

Private Attributes

Additional Inherited Members

Detailed Description

Constructor & Destructor Documentation

◆ Multiplexer()

◆ ~Multiplexer()

Member Function Documentation

◆ CoreIRGenFunctionality()

◆ createMRRG()

◆ GenericName()

◆ GenFunctionality()

◆ getBitConfig()

◆ getMuxSize()

Member Data Documentation

◆ mux_size