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Module Class Reference

#include <Module.h>

Inheritance diagram for Module:
AdresPE CaseStatement Compare ConfigCell ConstUnit ContextCell ContextCounter Crossbar CustomModule CustomModuleSingleInput DeMux DisconnectedSink DisconnectedSource ElasticBufferFifo ElasticCrossbar ElasticDiverge ElasticEagerFork ElasticForkBranch ElasticFPUnit ElasticFuncUnit ElasticJoin ElasticLazyFork ElasticMemoryUnit ElasticMemPort ElasticMerge ElasticRegisterFile ElasticSelMultiplexer ElasticTokenInducer ElasticVLUWrapper EventTransitionTable FPAdd FPDiv FPMult FPSqrt FPUnit FPUnit_wrapper FracAddUnit FracMulUnit FracUnit FuncUnit HyCUBEPE InputIEEE2FloPoCo IO IOPort MemoryUnit MemPort Multiplexer OutputConvert2FP OutputConvert2Int OutputFloPoCo2IEEE Register RegisterFile RIKEN_PE_Elastic SelMultiplexer SimpleFU TriState TruncateInput UserModule

Classes

struct  VisualPositionPoint
 
struct  VisualPositionRect
 

Public Member Functions

 Module (std::string name, Location, unsigned size=DEFAULT_SIZE, bool isElastic=false)
 
 Module (std::string name, std::string template_name, Location loc={0, 0}, unsigned size=DEFAULT_SIZE, bool isElastic=false)
 
virtual ~Module ()
 
 Module (const Module &)=delete
 
 Module (Module &&)=default
 
Module & operator= (const Module &)=delete
 
Module & operator= (Module &&)=default
 
void print ()
 
void print_dot ()
 
void print_ports ()
 
void print_connections ()
 
void print_submodules ()
 
void print_configcells ()
 
void addConfig (ConfigCell *c, std::vector< std::string > ConnectTo)
 
void addConfig (std::string name, std::vector< std::string > ConnectTo, int contexts, bool isElastic)
 
void addSubModule (Module *m)
 
void addSubModule (Module *m, double xPos, double yPos, double width, double height)
 
void connectPorts (std::string src, std::string dst, bool isElastic)
 
void addConnection (std::string src, std::string dst, bool isInMRRG=true)
 
void addElasticConnection (std::string src, std::string dst)
 
void addPort (std::string portname, port_type pt, unsigned size)
 
void addPort (std::string portname, port_type pt, unsigned size, bool isElastic)
 
void addElasticPort (std::string portname, port_type pt, unsigned size)
 
void addPort (std::string portname, port_type pt, std::string ParameterName, unsigned size)
 
void addPort (std::string portname, port_type pt, std::string ParameterName, unsigned size, bool isElastic)
 
void addElasticPort (std::string portname, port_type pt, std::string ParameterName, unsigned size)
 
void addParameter (std::string parameterName, unsigned parameterValue)
 
void addVerilogPort (std::string name, port_type pt, std::string parameter, unsigned size)
 
void genConfigOrder (std::vector< ConfigCell * > &ConfigTable) const
 
Module * getSubModule (std::string)
 
bool isSubModule (Module *)
 
Module * getModule (std::string, std::string err_context="")
 
Module * getModuleFromPortName (std::string full_port_name, std::string err_context="")
 
Port * getPort (std::string full_port_name, std::string err_context="")
 
int getSize () const
 
auto & getName () const
 
std::string ReturnPath () const
 
bool hasConfigCells () const
 
virtual BitConfig getBitConfig (const MRRG &mrrg, const OpGraph &og, const Mapping &map, const ConfigCell &ccell, const MRRGNodesFromOpNode &mrrg_nodes_from_op_node, const MRRGNodesFromValNode &mrrg_nodes_from_val_node) const
 
virtual std::string GenericName ()
 
virtual MRRG * createMRRG (unsigned contexts)
 
void genVerilogCGRAME (std::string dir)
 
void genVerilogCoreIR (std::string dir, int contexts)
 
void GetModulesToPrint (std::queue< Module * > &ToPrint, std::set< std::string > &PrintedModMap)
 
virtual void GenModuleVerilog ()
 
CoreIR::TypeGenFun makeCoreIRInterfaceGenerator ()
 
CoreIR::ModuleDefGenFun makeCoreIRModuleDefinitonGenerator ()
 
virtual void CoreIRGenModuleVerilog (CoreIR::Context *c, int contexts)
 
bool setNodePosition (const std::string &nodeName, double x, double y)
 
std::pair< bool, std::pair< double, double > > getSubModulePosition (const std::string &submodName)
 
std::pair< bool, std::pair< double, double > > getNodePosition (const std::string &nodeName)
 
bool addsSynchronousCircuitry () const
 

Public Attributes

std::map< std::string, unsigned > parameterlist
 
std::map< std::string, Port * > ports
 
std::map< Port *, Connection * > connections
 
std::map< std::string, Module * > submodules
 
std::map< std::string, ConfigCell * > configcells
 
std::vector< Port > portsToPropagate
 
double area = 0.
 
unsigned int hierarchyLevel = 0
 
bool isLastInHierarchy
 
bool isElastic = false
 
bool submodsSet
 
Location loc
 
int overridenFanoutCount = -1
 
Module * parent = nullptr
 

Protected Member Functions

void GetConfigsToPrint (std::queue< ConfigCell * > &q, std::set< unsigned > &uniq)
 
void GenModuleHeader (bool HasConfig, bool HasRegisters)
 
void GenParameters ()
 
void GenPortSpecs (bool HasConfig, bool HasRegisters)
 
virtual void GenConnections ()
 
virtual void GenFunctionality ()
 
void CoreIRGetModulesToPrint (std::queue< Module * > &ToPrint, std::set< std::string > &PrintedModMap)
 
virtual nlohmann::json CoreIRGenFunctionality ()
 
void GenerateMatrix (StringMatrix &Matrix)
 
void DetermineConnections (StringMatrix &Matrix, PrintList &WireList, PrintList &SubmodList, PrintList &AssignList)
 
virtual std::vector< ResolvedVeroligModuleParameter > ResolveVerilogParameters () const
 
int FindPortIndex (std::string PortName)
 
int FindSubmoduleIndex (std::string SubmoduleName)
 

Protected Attributes

unsigned data_size
 
std::string templateName
 
std::string name
 
std::map< std::string, VisualPositionRect > submodule_relative_position = {}
 
std::map< std::string, VisualPositionPoint > node_relative_position = {}
 
bool adds_synchronous_circuitry
 

Detailed Description

Definition at line 163 of file Module.h.

Constructor & Destructor Documentation

◆ Module() [1/4]

Module::Module ( std::string  name,
Location  loc,
unsigned  size = DEFAULT_SIZE,
bool  isElastic = false 
)

Definition at line 130 of file Module.cpp.

◆ Module() [2/4]

Module::Module ( std::string  name,
std::string  template_name,
Location  loc = {0,0},
unsigned  size = DEFAULT_SIZE,
bool  isElastic = false 
)

Definition at line 134 of file Module.cpp.

◆ ~Module()

Module::~Module ( )
virtual

Definition at line 150 of file Module.cpp.

◆ Module() [3/4]

Module::Module ( const Module &  )
delete

◆ Module() [4/4]

Module::Module ( Module &&  )
default

Member Function Documentation

◆ addConfig() [1/2]

void Module::addConfig ( ConfigCell *  c,
std::vector< std::string >  ConnectTo 
)

Definition at line 1087 of file Module.cpp.

◆ addConfig() [2/2]

void Module::addConfig ( std::string  name,
std::vector< std::string >  ConnectTo,
int  contexts,
bool  isElastic 
)

Definition at line 1077 of file Module.cpp.

◆ addConnection()

void Module::addConnection ( std::string  src,
std::string  dst,
bool  isInMRRG = true 
)

Definition at line 1241 of file Module.cpp.

◆ addElasticConnection()

void Module::addElasticConnection ( std::string  src,
std::string  dst 
)

Definition at line 1469 of file Module.cpp.

◆ addElasticPort() [1/2]

void Module::addElasticPort ( std::string  portname,
port_type  pt,
std::string  ParameterName,
unsigned  size 
)

Definition at line 1411 of file Module.cpp.

◆ addElasticPort() [2/2]

void Module::addElasticPort ( std::string  portname,
port_type  pt,
unsigned  size 
)

Definition at line 1440 of file Module.cpp.

◆ addParameter()

void Module::addParameter ( std::string  parameterName,
unsigned  parameterValue 
)

Definition at line 1503 of file Module.cpp.

◆ addPort() [1/4]

void Module::addPort ( std::string  portname,
port_type  pt,
std::string  ParameterName,
unsigned  size 
)

Definition at line 1388 of file Module.cpp.

◆ addPort() [2/4]

void Module::addPort ( std::string  portname,
port_type  pt,
std::string  ParameterName,
unsigned  size,
bool  isElastic 
)

Definition at line 1375 of file Module.cpp.

◆ addPort() [3/4]

void Module::addPort ( std::string  portname,
port_type  pt,
unsigned  size 
)

Definition at line 1354 of file Module.cpp.

◆ addPort() [4/4]

void Module::addPort ( std::string  portname,
port_type  pt,
unsigned  size,
bool  isElastic 
)

Definition at line 1341 of file Module.cpp.

◆ addsSynchronousCircuitry()

bool Module::addsSynchronousCircuitry ( ) const
inline

Does this module add the requirement for clocks, regardless of submodules? That is, to know if this module requires clock ports, a recursive search must be done. See moduleRequiresClockPorts in ModuleProcedures.h

Definition at line 367 of file Module.h.

◆ addSubModule() [1/2]

void Module::addSubModule ( Module *  m)

Definition at line 1124 of file Module.cpp.

◆ addSubModule() [2/2]

void Module::addSubModule ( Module *  m,
double  xPos,
double  yPos,
double  width,
double  height 
)

Definition at line 1140 of file Module.cpp.

◆ addVerilogPort()

void Module::addVerilogPort ( std::string  name,
port_type  pt,
std::string  parameter,
unsigned  size 
)

Definition at line 1515 of file Module.cpp.

◆ connectPorts()

void Module::connectPorts ( std::string  src,
std::string  dst,
bool  isElastic 
)

Definition at line 1232 of file Module.cpp.

◆ CoreIRGenFunctionality()

nlohmann::json Module::CoreIRGenFunctionality ( )
protectedvirtual

Reimplemented in Compare, CaseStatement, ContextCounter, EventTransitionTable, ConfigCell, CustomModuleSingleInput, CustomModule, DisconnectedSink, DisconnectedSource, TriState, RegisterFile, DeMux, SelMultiplexer, TruncateInput, Multiplexer, Register, MemoryUnit, FracAddUnit, FracMulUnit, ElasticConfigCell, ElasticMemoryUnit, ElasticRegisterFile, ElasticTokenInducer, FPUnit_wrapper, ElasticVLUWrapper, ElasticMerge, ElasticDiverge, ElasticJoin, ElasticLazyFork, ElasticSelMultiplexer, OutputConvert2FP, OutputConvert2Int, ElasticForkBranch, OutputFloPoCo2IEEE, InputIEEE2FloPoCo, ElasticEagerFork, FPSqrt, FPDiv, FPMult, ElasticBufferFifo, and FPAdd.

Definition at line 757 of file Module.cpp.

◆ CoreIRGenModuleVerilog()

void Module::CoreIRGenModuleVerilog ( CoreIR::Context *  c,
int  contexts 
)
virtual

Reimplemented in UserModule.

Definition at line 606 of file Module.cpp.

◆ CoreIRGetModulesToPrint()

void Module::CoreIRGetModulesToPrint ( std::queue< Module * > &  ToPrint,
std::set< std::string > &  PrintedModMap 
)
protected

◆ createMRRG()

MRRG * Module::createMRRG ( unsigned  contexts)
virtual

Reimplemented in Compare, EventTransitionTable, TriState, DeMux, SelMultiplexer, TruncateInput, Multiplexer, Register, ConstUnit, MemoryUnit, FracAddUnit, FracMulUnit, FuncUnit, ElasticMemoryUnit, ElasticTokenInducer, FPUnit_wrapper, ElasticVLUWrapper, ElasticMerge, ElasticDiverge, ElasticJoin, ElasticLazyFork, ElasticSelMultiplexer, FPUnit, OutputConvert2FP, OutputConvert2Int, ElasticForkBranch, ElasticEagerFork, and ElasticBufferFifo.

Definition at line 1520 of file Module.cpp.

◆ DetermineConnections()

void Module::DetermineConnections ( StringMatrix &  Matrix,
PrintList &  WireList,
PrintList &  SubmodList,
PrintList &  AssignList 
)
protected

Definition at line 765 of file Module.cpp.

◆ FindPortIndex()

int Module::FindPortIndex ( std::string  PortName)
protected

Definition at line 969 of file Module.cpp.

◆ FindSubmoduleIndex()

int Module::FindSubmoduleIndex ( std::string  SubmoduleName)
protected

Definition at line 983 of file Module.cpp.

◆ genConfigOrder()

void Module::genConfigOrder ( std::vector< ConfigCell * > &  ConfigTable) const

Definition at line 164 of file Module.cpp.

◆ GenConnections()

void Module::GenConnections ( )
protectedvirtual

Definition at line 720 of file Module.cpp.

◆ GenerateMatrix()

void Module::GenerateMatrix ( StringMatrix &  Matrix)
protected

Definition at line 742 of file Module.cpp.

◆ GenericName()

std::string Module::GenericName ( )
virtual

Reimplemented in Compare, CaseStatement, ContextCounter, ContextCell, EventTransitionTable, ConfigCell, UserModule, CustomModuleSingleInput, CustomModule, DisconnectedSink, DisconnectedSource, IO, TriState, Crossbar, RegisterFile, DeMux, SelMultiplexer, TruncateInput, Multiplexer, Register, ConstUnit, MemoryUnit, FracAddUnit, FracMulUnit, FracUnit, FuncUnit, ElasticConfigCell, ElasticMemoryUnit, ElasticMemPort, ElasticCrossbar, ElasticFPUnit, ElasticFuncUnit, ElasticRegisterFile, ElasticTokenInducer, FPUnit_wrapper, ElasticVLUWrapper, ElasticMerge, ElasticDiverge, ElasticJoin, ElasticLazyFork, FPUnit, ElasticSelMultiplexer, OutputConvert2FP, OutputConvert2Int, ElasticForkBranch, OutputFloPoCo2IEEE, InputIEEE2FloPoCo, ElasticEagerFork, FPSqrt, FPDiv, FPMult, ElasticBufferFifo, FPAdd, HyCUBEPE, SimpleFU, RIKEN_PE_Elastic, AdresPE, IOPort, and MemPort.

Definition at line 260 of file Module.cpp.

◆ GenFunctionality()

void Module::GenFunctionality ( )
protectedvirtual

Reimplemented in CaseStatement, CustomModuleSingleInput, CustomModule, DisconnectedSink, DisconnectedSource, TriState, RegisterFile, Multiplexer, Register, ConstUnit, and MemoryUnit.

Definition at line 736 of file Module.cpp.

◆ GenModuleHeader()

void Module::GenModuleHeader ( bool  HasConfig,
bool  HasRegisters 
)
protected

Definition at line 645 of file Module.cpp.

◆ GenModuleVerilog()

void Module::GenModuleVerilog ( )
virtual

Reimplemented in ConfigCell, and UserModule.

Definition at line 268 of file Module.cpp.

◆ GenParameters()

void Module::GenParameters ( )
protected

Definition at line 675 of file Module.cpp.

◆ GenPortSpecs()

void Module::GenPortSpecs ( bool  HasConfig,
bool  HasRegisters 
)
protected

Definition at line 684 of file Module.cpp.

◆ genVerilogCGRAME()

void Module::genVerilogCGRAME ( std::string  dir)

Definition at line 175 of file Module.cpp.

◆ genVerilogCoreIR()

void Module::genVerilogCoreIR ( std::string  dir,
int  contexts 
)

◆ getBitConfig()

virtual BitConfig Module::getBitConfig ( const MRRG &  mrrg,
const OpGraph &  og,
const Mapping &  map,
const ConfigCell &  ccell,
const MRRGNodesFromOpNode &  mrrg_nodes_from_op_node,
const MRRGNodesFromValNode &  mrrg_nodes_from_val_node 
) const
inlinevirtual

Reimplemented in Compare, ContextCell, EventTransitionTable, TriState, DeMux, SelMultiplexer, Multiplexer, Register, ConstUnit, MemoryUnit, FracAddUnit, FracMulUnit, FuncUnit, ElasticMemoryUnit, ElasticTokenInducer, FPUnit_wrapper, ElasticMerge, ElasticDiverge, ElasticJoin, ElasticLazyFork, FPUnit, ElasticSelMultiplexer, ElasticForkBranch, ElasticEagerFork, and ElasticBufferFifo.

Definition at line 257 of file Module.h.

◆ GetConfigsToPrint()

void Module::GetConfigsToPrint ( std::queue< ConfigCell * > &  q,
std::set< unsigned > &  uniq 
)
protected

Definition at line 240 of file Module.cpp.

◆ getModule()

Module * Module::getModule ( std::string  module_name,
std::string  err_context = "" 
)

Definition at line 1167 of file Module.cpp.

◆ getModuleFromPortName()

Module * Module::getModuleFromPortName ( std::string  full_port_name,
std::string  err_context = "" 
)

Definition at line 1186 of file Module.cpp.

◆ GetModulesToPrint()

void Module::GetModulesToPrint ( std::queue< Module * > &  ToPrint,
std::set< std::string > &  PrintedModMap 
)

Definition at line 220 of file Module.cpp.

◆ getName()

auto& Module::getName ( ) const
inline

Definition at line 247 of file Module.h.

◆ getNodePosition()

std::pair< bool, std::pair< double, double > > Module::getNodePosition ( const std::string &  nodeName)

Definition at line 1678 of file Module.cpp.

◆ getPort()

Port * Module::getPort ( std::string  full_port_name,
std::string  err_context = "" 
)

Definition at line 1201 of file Module.cpp.

◆ getSize()

int Module::getSize ( ) const
inline

Definition at line 246 of file Module.h.

◆ getSubModule()

Module * Module::getSubModule ( std::string  m)

Definition at line 1147 of file Module.cpp.

◆ getSubModulePosition()

std::pair< bool, std::pair< double, double > > Module::getSubModulePosition ( const std::string &  submodName)

Definition at line 1629 of file Module.cpp.

◆ hasConfigCells()

bool Module::hasConfigCells ( ) const
inline

Definition at line 255 of file Module.h.

◆ isSubModule()

bool Module::isSubModule ( Module *  subModule)

Definition at line 1160 of file Module.cpp.

◆ makeCoreIRInterfaceGenerator()

CoreIR::TypeGenFun Module::makeCoreIRInterfaceGenerator ( )

Definition at line 294 of file Module.cpp.

◆ makeCoreIRModuleDefinitonGenerator()

CoreIR::ModuleDefGenFun Module::makeCoreIRModuleDefinitonGenerator ( )

Definition at line 409 of file Module.cpp.

◆ operator=() [1/2]

Module& Module::operator= ( const Module &  )
delete

◆ operator=() [2/2]

Module& Module::operator= ( Module &&  )
default

◆ print()

void Module::print ( )

Definition at line 996 of file Module.cpp.

◆ print_configcells()

void Module::print_configcells ( )

Definition at line 1055 of file Module.cpp.

◆ print_connections()

void Module::print_connections ( )

Definition at line 1034 of file Module.cpp.

◆ print_dot()

void Module::print_dot ( )

Definition at line 1008 of file Module.cpp.

◆ print_ports()

void Module::print_ports ( )

Definition at line 1027 of file Module.cpp.

◆ print_submodules()

void Module::print_submodules ( )

Definition at line 1046 of file Module.cpp.

◆ ResolveVerilogParameters()

std::vector< ResolvedVeroligModuleParameter > Module::ResolveVerilogParameters ( ) const
protectedvirtual

Function to override parameters within a module during Verilog declaration. returns list of key-value pairs that will be part of the module instantiation. Provided implementation just scrapes this->parameterlist.

Definition at line 954 of file Module.cpp.

◆ ReturnPath()

std::string Module::ReturnPath ( ) const
inline

Definition at line 248 of file Module.h.

◆ setNodePosition()

bool Module::setNodePosition ( const std::string &  nodeName,
double  x,
double  y 
)

Definition at line 1671 of file Module.cpp.

Member Data Documentation

◆ adds_synchronous_circuitry

bool Module::adds_synchronous_circuitry
protected

Definition at line 370 of file Module.h.

◆ area

double Module::area = 0.

Definition at line 233 of file Module.h.

◆ configcells

std::map<std::string, ConfigCell*> Module::configcells

Definition at line 228 of file Module.h.

◆ connections

std::map<Port*, Connection*> Module::connections

Definition at line 226 of file Module.h.

◆ data_size

unsigned Module::data_size
protected

Definition at line 338 of file Module.h.

◆ hierarchyLevel

unsigned int Module::hierarchyLevel = 0

Definition at line 234 of file Module.h.

◆ isElastic

bool Module::isElastic = false

Definition at line 236 of file Module.h.

◆ isLastInHierarchy

bool Module::isLastInHierarchy

Definition at line 235 of file Module.h.

◆ loc

Location Module::loc

Definition at line 239 of file Module.h.

◆ name

std::string Module::name
protected

Definition at line 341 of file Module.h.

◆ node_relative_position

std::map<std::string, VisualPositionPoint> Module::node_relative_position = {}
protected

Definition at line 360 of file Module.h.

◆ overridenFanoutCount

int Module::overridenFanoutCount = -1

Definition at line 241 of file Module.h.

◆ parameterlist

std::map<std::string, unsigned> Module::parameterlist

Definition at line 224 of file Module.h.

◆ parent

Module* Module::parent = nullptr

Definition at line 243 of file Module.h.

◆ ports

std::map<std::string, Port*> Module::ports

Definition at line 225 of file Module.h.

◆ portsToPropagate

std::vector<Port> Module::portsToPropagate

Definition at line 229 of file Module.h.

◆ submodsSet

bool Module::submodsSet

Definition at line 237 of file Module.h.

◆ submodule_relative_position

std::map<std::string, VisualPositionRect> Module::submodule_relative_position = {}
protected

Definition at line 359 of file Module.h.

◆ submodules

std::map<std::string, Module*> Module::submodules

Definition at line 227 of file Module.h.

◆ templateName

std::string Module::templateName
protected

Definition at line 340 of file Module.h.

The documentation for this class was generated from the following files:
Generated on Fri Nov 17 2023 12:26:56 for CGRA-ME by   doxygen 1.8.17