TatumInterface.cpp

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/*******************************************************************************
 * The software programs comprising "CGRA-ME" and the documentation provided
 * with them are copyright by its authors and the University of Toronto. Only
 * non-commercial, not-for-profit use of this software is permitted without ex-
 * plicit permission. This software is provided "as is" with no warranties or
 * guarantees of support. See the LICENCE for more details. You should have re-
 * ceived a copy of the full licence along with this software. If not, see
 * <http://cgra-me.ece.utoronto.ca/license/>.
 ******************************************************************************/
 
#include <CGRA/TatumInterface.h>
 
#include <CGRA/GraphAlgorithms.h>
 
TatumInterface::TatumInterface(std::map<std::string, double>& t, PerfEngine* p)
    : timingModels(t)
    , parent(p)
{
}
 
// Shrunk the MRRG by merging all HW_WIRE nodes into edges
void TatumInterface::removeWireNodes(EdgeList& orig, EdgeList& reduced)
{
    std::vector<MRRG::NodeDescriptor> uniq;
    std::vector<MRRG::NodeDescriptor> nonWire; // MRRG nodes that are not HW_WIRE type
    EdgeList invOrig; // inverse of orig[src] giving snk, invOig[snk] gives src
 
    // create list of unique nodes
    for (auto it = orig.begin(); it != orig.end(); it++)
    {
        auto src = it->first;
        auto snk = it->second;
        std::vector<MRRG::NodeDescriptor> pair = {src, snk};
        for (auto i = 0; i < 2; i++)
        {
            if (std::find(uniq.begin(), uniq.end(), pair[i]) == uniq.end())
                uniq.push_back(pair[i]);
        }
    }
 
    // populate list of non-HW_WIRE nodes
    for (auto& n : uniq)
    {
        if (n->et != HW_WIRE)
            nonWire.push_back(n);
    }
 
    // construct invOrig
    for (auto it = orig.begin(); it != orig.end(); it++)
        invOrig.insert(std::pair<MRRG::NodeDescriptor, MRRG::NodeDescriptor> (it->second, it->first));
 
    // identify each non-wire node's non-wire source(s) and sink(s)
    for (auto& n : nonWire)
    {
        // find the source nodes
        if (invOrig.count(n) != 0) // has source node(s)
        {
            std::vector<MRRG::NodeDescriptor> srcs;
            auto begin = invOrig.lower_bound(n);
            auto end = invOrig.upper_bound(n);
            for (auto it = begin; it != end; it++)
            {
                srcs.push_back(it->second);
            }
            for (auto s : srcs)
            {
                // trace back to find first non-wire source
                while (s->et == HW_WIRE)
                    s = invOrig.find(s)->second;
                reduced.insert(std::pair<MRRG::NodeDescriptor, MRRG::NodeDescriptor> (s, n));
            }
        }
    }
 
    /*
    */
    // Dump MRRG dot of mapped result without wire nodes
    std::cout << "digraph ReducedMRRG {" << std::endl;
    for(auto it = reduced.begin(); it != reduced.end(); it = reduced.upper_bound(it->first))
    {
        auto i = it;
        while (i != reduced.upper_bound(it->first))
        {
            auto src = i->first;
            auto des = i->second;
            std::cout << "\"" << *src << "\" -> \"" << *des << "\";" << std::endl;
            i++;
        }
    }
    std::cout << "}\n" << std::endl;
    /*
    */
}
 
void TatumInterface::createTatumTimingGraph(EdgeList& m)
{
    // timing graph and name resolver constructor
    std::shared_ptr<TimingGraph> tg_(new tatum::TimingGraph());
    tg = tg_;
    std::shared_ptr<MRRGNameResolver> nr_(new MRRGNameResolver(*tg));
    nr = nr_;
    EdgeList mrrg;
    removeWireNodes(m, mrrg);
 
    clk = tg->add_node(NodeType::SOURCE);
    nr->set_node_name(clk, "CGRA_Clock");
 
    std::vector<MRRG::NodeDescriptor> created;
    for (auto it = mrrg.begin(); it != mrrg.end(); it++)
    {
        auto src = it->first;
        auto snk = it->second;
#define createNewOnly(n, l)                         \
{                                                   \
    if (std::find(l.begin(), l.end(), n) == l.end())\
    {                                               \
        createTGEntity(n);                          \
        connectTGClock(n);                          \
        l.push_back(n);                             \
    }                                               \
}
        createNewOnly(src, created);
        createNewOnly(snk, created);
#undef createNewOnly
        connectTGEntities(src, snk);
    }
 
    tg->levelize();
}
 
void TatumInterface::initializeTatumEngine(EdgeList& m)
{
    // construct delay calculator and timing constraints
    std::shared_ptr<tatum::FixedDelayCalculator> dc_(
        new tatum::FixedDelayCalculator(
            maxComb,
            setup,
            minComb,
            hold
        )
    );
    dc = dc_;
    std::shared_ptr<tatum::TimingConstraints> tc_(
        new tatum::TimingConstraints()
    );
    tc = tc_;
    clkDid = tc->create_clock_domain("CGRA_Clock");
    tc->set_clock_domain_source(clk, clkDid);
 
    // set constraints to target zero clock period
    tc->set_setup_constraint(clkDid, clkDid, Time(0.));
    tc->set_hold_constraint(clkDid, clkDid, Time(0.));
 
    // generate list of entities acting as driver of the kernel/benchmark
    std::vector<MRRG::NodeDescriptor> drivers;
    for (auto it = m.begin(); it != m.end(); it++)
    {
        // appends every source node
        auto src = it->first;
        auto match = std::find(drivers.begin(), drivers.end(), src);
        if (match == drivers.end())
            drivers.push_back(src);
    }
    for (auto it = m.begin(); it != m.end(); it++)
    {
        // leave list with nodes which are strictly sources
        auto snk = it->second;
        auto match = std::find(drivers.begin(), drivers.end(), snk);
        if (match != drivers.end())
            drivers.erase(match);
    }
 
    // mark these drivers' IPINs as constant generator constraints
    for (auto& d : drivers)
    {
        auto entity = mrrg2tg[d];
        for (auto& l : entity->ipins)
        {
            for (auto& ipin : l)
            {
                tc->set_constant_generator(ipin);
            }
        }
    }
 
    // mark mem unit data OPINs as constant generator constraints
    for (auto& n : memOut)
    {
        tc->set_constant_generator(n);
    }
 
    // construct analyzer and reporter object
    analyzer =
        tatum::AnalyzerFactory<tatum::SetupHoldAnalysis>::make(
            *tg,
            *tc,
            *dc
        );
    analyzer->update_timing();
    std::shared_ptr<tatum::TimingReporter> tr_(
        new tatum::TimingReporter(
            *nr,
            *tg,
            *tc
        )
    );
    tr = tr_;
}
 
void TatumInterface::reportSetupAnalysis()
{
    /*
    */
    auto dot_writer = tatum::make_graphviz_dot_writer(*tg, *dc);
    dot_writer.write_dot_file("/tmp/CGRAME_TatumTG.dot");
    tr->report_unconstrained_setup("/tmp/CGRAME_TimingReport_UnconstrainedSetupAnalysis.rpt", *analyzer);
    /*
    */
    cgrame_msg("Performing STA...");
    tr->report_timing_setup("/tmp/CGRAME_TimingReport_SetupAnalysis.rpt", *analyzer);
    cgrame_msg("STA completed. Report dumped to: `/tmp/CGRAME_TimingReport_SetupAnalysis.rpt`");
}
 
//void TatumInterface::reportHoldAnalysis()
//{
//    cgrame_msg("Performing STA...");
//    //tr->report_unconstrained_hold("/tmp/CGRAME_TimingReport_UnconstrainedHoldAnalysis.rpt", *analyzer);
//    tr->report_timing_hold("/tmp/CGRAME_TimingReport_HoldAnalysis.rpt", *analyzer);
//    cgrame_msg("STA completed. Report dumped to: `/tmp/CGRAME_TimingReport_HoldAnalysis.rpt`");
//}
 
void TatumInterface::createTGEntity(MRRG::NodeDescriptor n, bool reduce)
{
    // for brevity
    const auto ET_COMB = tatum::EdgeType::PRIMITIVE_COMBINATIONAL;
    const auto ET_INTERC = tatum::EdgeType::INTERCONNECT;
    const auto ET_C_LAUN = tatum::EdgeType::PRIMITIVE_CLOCK_LAUNCH;
    const auto ET_C_CAPT = tatum::EdgeType::PRIMITIVE_CLOCK_CAPTURE;
 
    std::string n_name = std::to_string(n->cycle) + ":" + n->name;
    switch (n->et)
    {
        case HW_REG:
        {
            // In Tatum, a flip-flop(1-bit) is modelled as such:
            //  ipin ──┐           ┌─> opin
            //         v           ╵
            //        sink <─┐┌─> source
            //               ╵╵
            //              cpin
            // where specific timing parameters are moddelled:
            //  setup:  cpin ─> sink
            //  hold:   cpin ─> sink
            //  clk2q:  source ─> opin
            //  skew:   *(external) ─> cpin
 
            // look up data size
            auto width = n->parent->getSize();
 
            std::shared_ptr<TGEntity> reg(new TGEntity);
            reg->type = TG_REG;
            reg->width = width;
            reg->parent = n;
            mrrg2tg[n] = reg;
 
            // look up timing parameters
            auto moduleName = n->parent->GenericName();
            size_t index = moduleName.find("_");
            auto moduleBasename = moduleName.substr(0, index);
            auto moduleSuffix = moduleName.substr(index + 1, moduleName.length());
            auto key = moduleBasename + "." + moduleSuffix;
            auto kSetup = key + ".setup";
            auto kHold = key + ".hold";
            auto kC2q = key + ".c2q";
            tatum::Time t_su, t_h, t_c2q;
            if (timingModels.count(kSetup) == 0)
                throw cgrame_error("Timing model of register type \"" + kSetup + "\" does not exist...");
            if (timingModels.count(kHold) == 0)
                throw cgrame_error("Timing model of register type \"" + kHold + "\" does not exist...");
            if (timingModels.count(kC2q) == 0)
                throw cgrame_error("Timing model of register type \"" + kC2q + "\" does not exist...");
            t_su = tatum::Time(timingModels[kSetup]);
            t_h = tatum::Time(timingModels[kHold]);
            t_c2q = tatum::Time(timingModels[kC2q]);
 
            std::vector<tatum::NodeId> empty;
            reg->ipins.push_back(empty);
 
            // Special case: ConstUnit's constant value registers are not
            // clocked by CGRA_Clock, and should be handled like hardcode
            // value which won't require any CPIN, SOURCE, or SINK node.
            if (n->type == MRRG_NODE_FUNCTION)
            {
                for (unsigned i = 0; i < (reduce?1:width); i++)
                {
                    auto ipin = tg->add_node(tatum::NodeType::IPIN);
                    auto opin = tg->add_node(tatum::NodeType::OPIN);
                    tg2mrrg[ipin] = n;
                    tg2mrrg[opin] = n;
                    nr->set_node_name(ipin, n_name + ".Q[" + std::to_string(i) + "] (" + moduleName + ")");
                    nr->set_node_name(opin, n_name + ".out[" + std::to_string(i) + "] (" + moduleName + ")");
                    auto ipin2opin = tg->add_edge(ET_INTERC, ipin, opin);
                    reg->ipins[0].push_back(ipin);
                    reg->opins.push_back(opin);
                    reg->ipins2opins.push_back(ipin2opin);
                    maxComb.insert(ipin2opin, tatum::Time(0.));
                    minComb.insert(ipin2opin, tatum::Time(0.));
                }
 
                break;
            }
 
 
            // create the timing graph of this entity
            for (unsigned i = 0; i < (reduce?1:width); i++)
            {
                // create Tatum timing graph nodes
                auto ipin = tg->add_node(tatum::NodeType::IPIN);
                auto opin = tg->add_node(tatum::NodeType::OPIN);
                auto cpin = tg->add_node(tatum::NodeType::CPIN);
                auto src = tg->add_node(tatum::NodeType::SOURCE);
                auto snk = tg->add_node(tatum::NodeType::SINK);
                tg2mrrg[ipin] = n;
                tg2mrrg[opin] = n;
                tg2mrrg[cpin] = n;
                tg2mrrg[src] = n;
                tg2mrrg[snk] = n;
                nr->set_node_name(ipin, n_name + ".D[" + std::to_string(i) + "] (" + moduleName + ")");
                nr->set_node_name(opin, n_name + ".Q[" + std::to_string(i) + "] (" + moduleName + ")");
                nr->set_node_name(cpin, n_name + ".clk");
                nr->set_node_name(snk, n_name + ".D_sink[" + std::to_string(i) + "] (" + moduleName + ")");
                nr->set_node_name(src, n_name + ".Q_source[" + std::to_string(i) + "] (" + moduleName + ")");
 
                // create Tatum timing graph edges
                auto ipin2snk = tg->add_edge(ET_COMB, ipin, snk);
                auto src2opin = tg->add_edge(ET_C_LAUN, src, opin);
                auto cpin2snk = tg->add_edge(ET_C_CAPT, cpin, snk);
                auto cpin2src = tg->add_edge(ET_COMB, cpin, src);
 
                reg->ipins[0].push_back(ipin);
                reg->opins.push_back(opin);
                reg->cpins.push_back(cpin);
                reg->srcs.push_back(src);
                reg->snks.push_back(snk);
                reg->ipins2snks.push_back(ipin2snk);
                reg->srcs2opins.push_back(src2opin);
                reg->cpins2snks.push_back(cpin2snk);
                reg->cpins2srcs.push_back(cpin2src);
 
                // fill in timing parameters
                setup.insert(cpin2snk, t_su);
                hold.insert(cpin2snk, t_h);
                maxComb.insert(cpin2src, tatum::Time(0.));
                minComb.insert(cpin2src, tatum::Time(0.));
                maxComb.insert(ipin2snk, tatum::Time(0.));
                minComb.insert(ipin2snk, tatum::Time(0.));
                maxComb.insert(src2opin, t_c2q); // t_clk2q
                minComb.insert(src2opin, t_c2q); // t_clk2q
            }
            break;
        }
        case HW_MUX:
        {
            // TODO/FIXME: for realistic modelling, config storage driving
            // select signals should also be added
 
            // look up data size
            auto width = n->parent->getSize();
 
            std::shared_ptr<TGEntity> mux(new TGEntity);
            mux->type = TG_COMB;
            mux->width = width;
            mux->parent = n;
            mrrg2tg[n] = mux;
 
            // look up timing parameters
            auto moduleName = n->parent->GenericName();
            size_t index = moduleName.find("_");
            auto moduleBasename = moduleName.substr(0, index);
            auto moduleSuffix = moduleName.substr(index + 1, moduleName.length());
            auto key = moduleBasename + "." + moduleSuffix;
            tatum::Time t_max, t_min; // max and min combinational delay
            // TODO: min & max should use separate key
            if (timingModels.count(key) == 0)
                throw cgrame_error("Timing model of multiplexor type \"" + key + "\" does not exist...");
            t_max = tatum::Time(timingModels[key]);
            t_min = tatum::Time(timingModels[key]);
 
            std::vector<tatum::NodeId> empty;
            mux->ipins.push_back(empty);
 
            // create the timing graph of this entity
            for (unsigned i = 0; i < (reduce?1:width); i++)
            {
                // create TG nodes and edges
                auto ipin = tg->add_node(tatum::NodeType::IPIN);
                auto opin = tg->add_node(tatum::NodeType::OPIN);
                tg2mrrg[ipin] = n;
                tg2mrrg[opin] = n;
                // FIXME: figure out which input index is being used (assumed 0 for now)
                nr->set_node_name(ipin, n_name + ".in0[" + std::to_string(i) + "] (" + moduleName + ")");
                nr->set_node_name(opin, n_name + ".out[" + std::to_string(i) + "] (" + moduleName + ")");
                auto ipin2opin = tg->add_edge(ET_COMB, ipin, opin);
                mux->ipins[0].push_back(ipin);
                mux->opins.push_back(opin);
                mux->ipins2opins.push_back(ipin2opin);
 
                // fill in timing parameters
                maxComb.insert(ipin2opin, t_max);
                minComb.insert(ipin2opin, t_min);
            }
            break;
        }
        case HW_COMB:
        {
            auto moduleName = n->parent->GenericName();
 
            //retrieve op information from MRRGNode
            // could either be an ALU op or a memory op
            std::vector<OpGraphOpCode> aluOps =
            {
                OpCode::ADD,
                OpCode::SUB,
                OpCode::MUL,
                OpCode::DIV,
                OpCode::AND,
                OpCode::OR,
                OpCode::XOR,
                OpCode::SHL,
                OpCode::ASHR,
                OpCode::LSHR,
            };
            std::vector<OpGraphOpCode> memOps =
            {
                OpCode::LOAD,
                OpCode::STORE,
            };
 
            //auto opCode = n->mapped_opcode;
            auto opCode = parent->mapped_node2opcode[n];
            auto opName = to_string(opCode);
            auto width = n->parent->getSize();
            auto key = opName + "_" + std::to_string(width) + "b";
            if (std::find(aluOps.begin(), aluOps.end(), opCode) != aluOps.end())
            {
                // TODO: latency of ALU is currently unused on the mapper side,
                // so this portion of code will need update once mapper does
                // fully support latency specification.
                // TODO: should have t_comb_max and t_comb_min
                std::shared_ptr<TGEntity> fu(new TGEntity);
                fu->type = TG_COMB;
                fu->width = width;
                fu->parent = n;
                mrrg2tg[n] = fu;
                tatum::Time t_comb;
                key = "op." + key;
                if (timingModels.count(key) == 0)
                    throw cgrame_error("Timing model of compute unit type \"" + key + "\" does not exist...");
                t_comb = tatum::Time(timingModels[key]);
 
                std::vector<tatum::NodeId> ipinsA;
                std::vector<tatum::NodeId> ipinsB;
                fu->ipins.push_back(ipinsA);
                fu->ipins.push_back(ipinsB);
 
                // create fully connected in[*]->out[*]
                std::vector<tatum::NodeId> opins;
                for (unsigned i = 0; i < (reduce?1:width); i++)
                {
                    auto opin = tg->add_node(tatum::NodeType::OPIN);
                    opins.push_back(opin);
                    tg2mrrg[opin] = n;
                    nr->set_node_name(opin, n_name + ".out[" + std::to_string(i) + "] (" + moduleName + ")");
                    fu->opins.push_back(opin);
                }
                for (unsigned i = 0; i < (reduce?1:width); i++)
                {
                    auto ipinA = tg->add_node(tatum::NodeType::IPIN);
                    auto ipinB = tg->add_node(tatum::NodeType::IPIN);
                    tg2mrrg[ipinA] = n;
                    tg2mrrg[ipinB] = n;
                    nr->set_node_name(ipinA, n_name + ".in_a[" + std::to_string(i) + "] (" + moduleName + ")");
                    nr->set_node_name(ipinB, n_name + ".in_b[" + std::to_string(i) + "] (" + moduleName + ")");
                    fu->ipins[0].push_back(ipinA);
                    fu->ipins[1].push_back(ipinB);
                    for (unsigned j = 0; j < (reduce?1:width); j++)
                    {
                        auto ipinA2opin = tg->add_edge(ET_COMB, ipinA, opins[j]);
                        auto ipinB2opin = tg->add_edge(ET_COMB, ipinB, opins[j]);
                        fu->ipins2opins.push_back(ipinA2opin);
                        fu->ipins2opins.push_back(ipinB2opin);
                        maxComb.insert(ipinA2opin, t_comb);
                        minComb.insert(ipinA2opin, t_comb);
                        maxComb.insert(ipinB2opin, t_comb);
                        minComb.insert(ipinB2opin, t_comb);
                    }
                }
            }
            else if (std::find(memOps.begin(), memOps.end(), opCode) != memOps.end())
            {
                std::shared_ptr<TGEntity> mem(new TGEntity);
                mem->type = TG_COMB;
                mem->width = width;
                mem->parent = n;
                mrrg2tg[n] = mem;
                tatum::Time t_acc;
                key = "memUnit." + key;
                if (timingModels.count(key) == 0)
                    throw cgrame_error("Timing model of memory unit \"" + key + "\" does not exist...");
                t_acc = tatum::Time(timingModels[key]);
                if (opCode == OpCode::LOAD)
                {
                    std::vector<tatum::NodeId> empty;
                    mem->ipins.push_back(empty);
                    for (unsigned i = 0; i < (reduce?1:width); i++)
                    {
                        // TODO: currently ipin[i] points to opin[i], we should
                        // make sure this TG representation is acceptable
                        auto ipin = tg->add_node(tatum::NodeType::IPIN);
                        auto opin = tg->add_node(tatum::NodeType::OPIN);
                        tg2mrrg[ipin] = n;
                        tg2mrrg[opin] = n;
                        nr->set_node_name(ipin, n_name + ".addr[" + std::to_string(i) + "] (" + moduleName + ")");
                        nr->set_node_name(opin, n_name + ".out[" + std::to_string(i) + "] (" + moduleName + ")");
 
                        //FIXME: remove any use for memOut once OpenRAM results are in
                        //auto ipin2opin = tg->add_edge(ET_COMB, ipin, opin);
                        memOut.push_back(opin);
 
                        mem->ipins[0].push_back(ipin);
                        mem->opins.push_back(opin);
                        //mem->ipins2opins.push_back(ipin2opin);
 
                        // fill in timing parameters
                        //maxComb.insert(ipin2opin, t_acc);
                        //minComb.insert(ipin2opin, t_acc);
                    }
                }
                else if (opCode == OpCode::STORE)
                {
                    std::vector<tatum::NodeId> ipinsAddr;
                    std::vector<tatum::NodeId> ipinsData;
                    mem->ipins.push_back(ipinsAddr);
                    mem->ipins.push_back(ipinsData);
                    for (unsigned i = 0; i < (reduce?1:width); i++)
                    {
                        auto ipinAddr = tg->add_node(tatum::NodeType::IPIN);
                        auto opinAddr = tg->add_node(tatum::NodeType::OPIN);
                        auto ipinData = tg->add_node(tatum::NodeType::IPIN);
                        auto opinData = tg->add_node(tatum::NodeType::OPIN);
                        nr->set_node_name(ipinAddr, n_name + ".addr[" + std::to_string(i) + "] (" + moduleName + ")");
                        nr->set_node_name(opinAddr, n_name + ".extAddr[" + std::to_string(i) + "] (" + moduleName + ")");
                        nr->set_node_name(ipinData, n_name + ".data[" + std::to_string(i) + "] (" + moduleName + ")");
                        nr->set_node_name(opinData, n_name + ".extData[" + std::to_string(i) + "] (" + moduleName + ")");
                        tg2mrrg[ipinAddr] = n;
                        tg2mrrg[opinAddr] = n;
                        tg2mrrg[ipinData] = n;
                        tg2mrrg[opinData] = n;
                        auto ipin2opinAddr = tg->add_edge(ET_COMB, ipinAddr, opinAddr);
                        auto ipin2opinData = tg->add_edge(ET_COMB, ipinData, opinData);
                        mem->ipins[0].push_back(ipinAddr);
                        mem->ipins[1].push_back(ipinData);
                        mem->opins.push_back(opinAddr);
                        mem->opins.push_back(opinData);
                        mem->ipins2opins.push_back(ipin2opinAddr);
                        mem->ipins2opins.push_back(ipin2opinData);
 
                        // fill in timing parameters
                        maxComb.insert(ipin2opinAddr, t_acc);
                        minComb.insert(ipin2opinAddr, t_acc);
                        maxComb.insert(ipin2opinData, t_acc);
                        minComb.insert(ipin2opinData, t_acc);
                    }
                }
                else
                    throw cgrame_error("Non-load/store operation mapped to a memUnit");
            } else if (opCode == OpCode::OUTPUT) {
                // not sure if this the correct way to model IO
                auto io = std::make_shared<TGEntity>();
                io->type = TG_COMB;
                io->width = width;
                io->parent = n;
                mrrg2tg[n] = io;
 
                auto ipin = tg->add_node(tatum::NodeType::IPIN);
                nr->set_node_name(ipin, n_name + " output pin");
                tg2mrrg[ipin] = n;
 
                io->ipins.emplace_back();
                io->ipins.at(0).push_back(ipin);
            } else if (opCode == OpCode::INPUT) {
                // not sure if this the correct way to model IO
                auto io = std::make_shared<TGEntity>();
                io->type = TG_COMB;
                io->width = width;
                io->parent = n;
                mrrg2tg[n] = io;
 
                auto opin = tg->add_node(tatum::NodeType::OPIN);
                nr->set_node_name(opin, n_name + " input pin");
                tg2mrrg[opin] = n;
 
                io->opins.push_back(opin);
            }
            else
                throw cgrame_error("Unexpected non-routing combinational entity");
            break;
        }
        case HW_WIRE:
            // NOTE: wires are transformed/merged into mere MRRG edges and
            // shouldn't be encountered in this method, refer to class method
            // removeWireNodes() within method createTatumTimingGraph().
            throw cgrame_error("Wire entity is not a valid timing graph node");
            break;
        case HW_UNSPECIFIED:
            throw cgrame_error("MRRG node is of unspecified HW entity");
            break;
    }
}
 
void TatumInterface::connectTGEntities(MRRG::NodeDescriptor src, MRRG::NodeDescriptor snk, bool reduce)
{
    auto tg_src = mrrg2tg.at(src);
    auto tg_snk = mrrg2tg.at(snk);
 
    std::string src_name = std::to_string(src->cycle) + ":" + src->name;
    std::string snk_name = std::to_string(snk->cycle) + ":" + snk->name;
 
    unsigned width;
    unsigned in_index;
 
    if (snk->et == HW_COMB && tg_snk->used_input > 1)
        throw cgrame_error("All ports of fanout hardware `" + snk_name + "` are assigned");
    else
        in_index = tg_snk->used_input;
 
    if (tg_src->width != tg_snk->width)
        throw cgrame_error("Edges can't be made between entities of different data width");
    else
        width = tg_src->width;
 
    tg_snk->used_input++; //FIXME: hacky mechanism to choose which ipins
 
    double est_RC_delay = getFanoutBasedRCDelay(src);
 
    for (unsigned i = 0; i < (reduce?1:width); i++)
    {
        // FIXME: currently, this doesn't check which input is for inputA/B in
        // FuncUnit case, and it also doesn't check which input addr/data in
        // MEMUnit case.
        auto wire = tg->add_edge(tatum::EdgeType::INTERCONNECT, tg_src->opins[i], tg_snk->ipins[in_index][i]);
        maxComb.insert(wire, tatum::Time(est_RC_delay)); //FIXME: should be part of user input
        minComb.insert(wire, tatum::Time(est_RC_delay)); //FIXME: should be part of user input
    }
}
 
// DF traversal on fanout list locating all fanout primitives
std::set<MRRG::NodeDescriptor> getFanoutPrimitives(MRRG::NodeDescriptor s)
{
    struct LocalMRRG {
        auto& fanout(MRRG::NodeDescriptor n) const { return n->fanout; }
    } mrrg;
 
    struct V : DoNothingGraphVisitor<MRRG::NodeDescriptor> {
        Module* starting_module;
        std::set<MRRG::NodeDescriptor> found_non_wires;
 
        // records any nodes with significant delay (ie. aren't wires)
        void onExamine(const MRRG::NodeDescriptor& v) {
            if (v->parent != starting_module and v->et != HW_WIRE) {
                found_non_wires.insert(v);
            }
        }
 
        // don't explore beyond any nodes as found in onExamine
        bool shouldIgnoreEdge(const MRRG::NodeDescriptor& source, const MRRG::NodeDescriptor&) {
            return found_non_wires.find(source) != found_non_wires.end();
        }
    } v;
    v.starting_module = s->parent;
 
    GraphAlgorithms<MRRG::NodeDescriptor> g_algos;
    g_algos.depthFirstVisit(mrrg, s, visitAllVertices(), v);
 
    return std::move(v.found_non_wires);
}
 
double TatumInterface::getFanoutBasedRCDelay(MRRG::NodeDescriptor src)
{
    double delay = 0.;
    Module* src_module = src->parent;
    std::vector<MRRG::NodeDescriptor> fanout_nodes;
    std::vector<MRRG::NodeDescriptor> false_path_checklist;
 
    getFanoutPrimitives(src);
 
    auto overriden = src_module->overridenFanoutCount;
    auto fanoutCount = (overriden == -1) ? fanout_nodes.size() : overriden;
    auto base = timingModels["wireload.base"];
    auto scale = timingModels["wireload.scale"];
    delay = scale * (double)fanoutCount + base;
 
    return delay;
}
 
void TatumInterface::connectTGClock(MRRG::NodeDescriptor n, bool reduce)
{
    auto tg_entity = mrrg2tg[n];
    if (n->et == HW_REG && n->type != MRRG_NODE_FUNCTION)
    {
        auto len = tg_entity->cpins.size();
        for (auto i = 0; i < (reduce?1:len); i++)
        {
            tatum::Time t_skew = tatum::Time(0.); //FIXME: should be part of user input
            auto clkWire = tg->add_edge(EdgeType::INTERCONNECT, clk, tg_entity->cpins[i]);
            maxComb.insert(clkWire, t_skew);
            minComb.insert(clkWire, t_skew);
        }
    }
}