CGRA-ME
Control.cpp
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1 #include <CGRA/Control.h>
2 #include <math.h>
3 #include <cmath>
4 
5 using std::vector;
6 using std::ofstream;
7 using std::string;
8 using std::to_string;
9 
10 void buildComp(ofstream &myfile, std::vector<std::string> ports, int mem_size) {
11  string parameter[4] = {"INSTR_RDATA_WIDTH", "BOOT_ADDR", "PULP_SECURE", "A_EXTENSION"};
12  string input[10] = {"clk_i", "rst_ni","fetch_enable_i", "Config_Clock_en", "Config_Reset", "CGRA_Clock_en",
13  "CGRA_Reset", "riscv_enable", "configurator_enable", "configurator_reset"};
14  string logic[44] = {"riscv_rst_n", "counter", "instr_req", "instr_gnt", "instr_rvalid", "instr_addr", "instr_rdata",
15  "data_req", "data_gnt", "data_rvalid", "data_addr", "data_we", "data_be", "data_rdata", "data_wdata",
16  "data_rdata_port", "data_rdata_ram", "data_atop", "debug_req_i", "sec_lvl_o", "irq_ack", "irq_id",
17  "irq_sec", "irq_software","irq_timer", "irq_external", "irq_fast", "irq_nmi", "irq_fastx",
18  "ConfigIn", "ConfigOut", "CGRA_Enable", "cgra_data_addr", "cgra_data_rdata", "cgra_data_wdata",
19  "cgra_we_i", "core_busy_o", "Config_Clock", "CGRA_Reset_Control", "cgra_io", "select_port", "end_port",
20  "use_counter", "end_cgra"};
21  int mem_index;
22  std::vector<std::string> io_in_s;
23  std::vector<std::string> io_out_s;
24  std::vector<std::string> data_in_s;
25  std::vector<std::string> data_out_s;
26  std::vector<std::string> w_rq_s;
27  std::vector<std::string> addr_s;
28  for (auto port : ports) {
29  if (port.find("addr_to_ram") != string::npos) {
30  addr_s.push_back(port);
31  } else if (port.find("data_in_to_ram") != string::npos) {
32  data_in_s.push_back(port);
33  } else if (port.find("data_out_from_ram") != string::npos) {
34  data_out_s.push_back(port);
35  } else if (port.find("w_rq_to_ram") != string::npos) {
36  w_rq_s.push_back(port);
37  } else if (port.find("bidir_in") != string::npos) {
38  io_in_s.push_back(port);
39  } else if (port.find("bidir_out") != string::npos) {
40  io_out_s.push_back(port);
41  } /*else {
42  std::cout << "ports not for memory or I/O detected" << port << std::endl;
43  }*/
44  }
45  if (addr_s.size() != w_rq_s.size() || addr_s.size() != data_in_s.size() ||
46  addr_s.size() != data_out_s.size() || io_in_s.size() != io_out_s.size()) {
47  std::cout << "Port numbers are not consistent" << std::endl;
48  std::cout << addr_s.size() << " " << w_rq_s.size() << " " << data_in_s.size() << " " << data_in_s.size() << " " << io_in_s.size() << " " << io_out_s.size() << "\n";
49  exit(1);
50  }
51  if(!IsPowerOfTwo(addr_s.size())) {
52  std::cout << "Memory port number is not power of 2" << std::endl;
53  exit(1);
54  }
55 
56  std::vector<std::string> head_mem;
57  std::vector<std::string> head_io;
58  string::size_type pos;
59  for (auto port : addr_s) {
60  pos = port.find("mem_unit_addr_to_ram");
61  if (pos != string::npos) {
62  head_mem.push_back(port.substr(0, pos-1));
63  }
64  }
65  for (auto port : io_in_s) {
66  pos = port.find("IOPin_bidir_in");
67  if (pos != string::npos) {
68  head_io.push_back(port.substr(0, pos-1));
69  }
70  }
71 
72  vector<vector<string>> io_port;
73  vector<vector<string>> mem_port;
74  for (int i = 0; i < io_in_s.size(); i++) {
75  io_port.push_back(vector<string>());
76  io_port[i].push_back(io_in_s[i]);
77  io_port[i].push_back(io_out_s[i]);
78  }
79  for (int i = 0; i < addr_s.size(); i++) {
80  mem_port.push_back(vector<string>());
81  mem_port[i].push_back(addr_s[i]);
82  mem_port[i].push_back(data_in_s[i]);
83  mem_port[i].push_back(data_out_s[i]);
84  mem_port[i].push_back(w_rq_s[i]);
85  }
86  mem_index = mem_size - 1;
87  buildControl(myfile, io_port, mem_port, parameter, input, logic, mem_index);
88  buildRam(myfile, mem_port.size(), parameter, input, logic, mem_index);
89  ofstream header;
90  header.open("hybrid.h");
91  buildHybridHeader(header, head_mem, head_io);
92  header.close();
93  myfile.close();
94 }
95 
96 void buildControl(ofstream &myfile, vector<vector<string>> io_port, vector<vector<string>> mem_port,
97 string *parameter, string *input, string *logic, int mem_index) {
98  myfile << "module hybrid_wrapper\n";
99  myfile <<"\t#(parameter " << parameter[0] << " = 128,\n";
100  myfile <<"\tparameter " << parameter[1] << " = 'h180,\n";
101  myfile <<"\tparameter " << parameter[2] << " = 1,\n";
102  myfile <<"\tparameter " << parameter[3] << " = 1)\n";
103  myfile <<"\t(input logic " << input[0] << ",\n";
104  myfile <<"\tinput logic " << input[1] << ",\n";
105  myfile <<"\tinput logic " << input[2] << ",\n";
106  myfile <<"\tinput logic " << input[3] << ",\n";
107  myfile <<"\tinput logic " << input[4] << ",\n";
108  myfile <<"\tinput logic " << input[5] << ",\n";
109  myfile <<"\tinput logic " << input[6] << ",\n";
110  myfile <<"\tinput logic " << input[7] << ",\n";
111  myfile <<"\tinput logic " << input[8] << ",\n";
112  myfile <<"\tinput logic " << input[9] << ",\n";
113  myfile <<"\toutput logic configurator_done\n";
114  myfile <<"\t);\n\n";
115  myfile <<"\tlogic " << logic[0] << ";\n";
116  myfile <<"\tlogic [31:0] " << logic[1] << ";\n";
117  myfile <<"\tlogic " << logic[2] << ";\n";
118  myfile <<"\tlogic " << logic[3] << ";\n";
119  myfile <<"\tlogic " << logic[4] << ";\n";
120  myfile <<"\tlogic [31:0] " << logic[5] << ";\n";
121  myfile <<"\tlogic [" << parameter[0] << "-1:0] " << logic[6] << ";\n";
122  myfile <<"\tlogic " << logic[7] << ";\n";
123  myfile <<"\tlogic " << logic[8] << ";\n";
124  myfile <<"\tlogic " << logic[9] << ";\n";
125  myfile <<"\tlogic [31:0] " << logic[10] << ";\n";
126  myfile <<"\tlogic " << logic[11] << ";\n";
127  myfile <<"\tlogic [3:0] " << logic[12] << ";\n";
128  myfile <<"\tlogic [31:0] " << logic[13] << ";\n";
129  myfile <<"\tlogic [31:0] " << logic[14] << ";\n";
130  myfile <<"\tlogic [31:0] " << logic[15] << ";\n";
131  myfile <<"\tlogic [31:0] " << logic[16] << ";\n";
132  myfile <<"\tlogic [5:0] " << logic[17] << ";\n";
133  myfile <<"\tlogic " << logic[18] << ";\n";
134  myfile <<"\tlogic " << logic[19] << ";\n";
135  myfile <<"\tlogic " << logic[20] << ";\n";
136  myfile <<"\tlogic [0:4] " << logic[21] << ";\n";
137  myfile <<"\tlogic " << logic[22] << ";\n";
138  myfile <<"\tlogic " << logic[23] << ";\n";
139  myfile <<"\tlogic " << logic[24] << ";\n";
140  myfile <<"\tlogic " << logic[25] << ";\n";
141  myfile <<"\tlogic [14:0] " << logic[26] << ";\n";
142  myfile <<"\tlogic " << logic[27] << ";\n";
143  myfile <<"\tlogic [31:0] " << logic[28] << ";\n";
144  myfile <<"\tlogic " << logic[29] << ";\n";
145  myfile <<"\tlogic " << logic[30] << ";\n";
146  myfile <<"\tlogic " << logic[31] << ";\n";
147  myfile <<"\tlogic " << logic[36] << ";\n";
148  myfile <<"\tlogic " << logic[37] << ";\n";
149  myfile <<"\tlogic " << logic[38] << ";\n";
150  for(int i = 0; i < io_port.size(); i++) {
151  myfile <<"\tlogic [31:0] " << io_port[i][0] << ";\n";
152  myfile <<"\tlogic [31:0] " << io_port[i][1] << ";\n";
153  }
154  for(int i = 0; i < mem_port.size(); i++) {
155  myfile <<"\tlogic [31:0] " << mem_port[i][0] << ";\n";
156  myfile <<"\tlogic [31:0] " << mem_port[i][1] << ";\n";
157  myfile <<"\tlogic [31:0] " << mem_port[i][2] << ";\n";
158  myfile <<"\tlogic " << mem_port[i][3] << ";\n";
159  }
160  int bit = 32 * mem_port.size() - 1;
161  myfile <<"\tlogic [31:0] " << logic[32] << "[" << mem_port.size() - 1 << ":0];\n";
162  myfile <<"\tlogic [" << bit << ":0] " << logic[33] << ";\n";
163  myfile <<"\tlogic [31:0] " << logic[34] << "[" << mem_port.size() - 1 << ":0];\n";
164  myfile <<"\tlogic [" << mem_port.size() - 1 << ":0] " << logic[35] << ";\n";
165  myfile <<"\tlogic [31:0] " << logic[39] << "[" << io_port.size() - 1 << ":0];\n";
166  myfile <<"\tlogic [" << (int)ceil(log2(io_port.size())) << ":0] " << logic[40] << ";\n";
167  myfile <<"\tlogic [31:0] " << logic[41] << ";\n";
168  myfile <<"\tlogic " << logic[42] << ";\n";
169  myfile <<"\tlogic " << logic[43] << ";\n";
170  myfile <<"\tassign " << logic[37] << " = " << input[0] << " & " << input[3] << ";\n";
171  myfile <<"\tassign " << logic[0] << " = " <<input[1] << " & " << input[7] << ";\n";
172  myfile << "\tassign " << logic[35] << " = {\n";
173  for (int i = mem_port.size() - 1; i > 0; i--) {
174  myfile <<"\t\t" << mem_port[i][3] << ",\n";
175  }
176  myfile <<"\t\t" << mem_port[0][3] << "};\n\n";
177 
178  myfile <<"\tassign " << logic[41] << " = " << logic[39] << "[" << logic[40] << "];\n";
179  myfile << "\tassign " << logic[39] << " = {\n";
180  for (int i = io_port.size() - 1; i > 0; i--) {
181  myfile <<"\t\t" << io_port[i][1] << ",\n";
182  }
183  myfile <<"\t\t" << io_port[0][1] << "};\n\n";
184 
185  myfile << "\talways_comb begin\n\t\t" << logic[32] << " = {\n";
186  for (int i = mem_port.size() - 1; i > 0; i--) {
187  myfile <<"\t\t" << mem_port[i][0] << ",\n";
188  }
189  myfile <<"\t\t" << mem_port[0][0] << "};\n";
190  myfile << "\t\t{\n";
191  for (int i = mem_port.size() - 1; i > 0; i--) {
192  myfile <<"\t\t" << mem_port[i][2] << ",\n";
193  }
194  myfile <<"\t\t" << mem_port[0][2] << "} = " << logic[33] << ";\n";
195  myfile << "\t\t" << logic[34] << " = {\n";
196  for (int i = mem_port.size() - 1; i > 0; i--) {
197  myfile <<"\t\t" << mem_port[i][1] << ",\n";
198  }
199  myfile <<"\t\t" << mem_port[0][1] << "};\n";
200  myfile << "\tend\n\tassign " << logic[18] << " = 1'b0;\n\tassign " << logic[22] << " = 1'b0;\n\n";
201 
202  myfile << "\triscv_core\n";
203  myfile << "\t\t#(." << parameter[0] << " (" << parameter[0] << "),\n";
204  myfile << "\t\t." << parameter[2] << "(" << parameter[2] << "),\n";
205  myfile << "\t\t." << parameter[3] << "(" << parameter[3] << "),\n";
206  myfile << "\t\t.FPU(0))\n";
207  myfile << "\triscv_core_i (\n";
208  myfile << "\t\t." << input[0] << "(" << input[0] << "),\n";
209  myfile << "\t\t." << input[1] << "(" << logic[0] << "),\n";
210  myfile << "\t\t.clock_en_i('1),\n";
211  myfile << "\t\t.test_en_i('0),\n";
212  myfile << "\t\t.boot_addr_i(" << parameter[1] << "),\n";
213  myfile << "\t\t.core_id_i(4'h0),\n";
214  myfile << "\t\t.cluster_id_i(6'h0),\n";
215  myfile << "\t\t." << logic[5] << "_o(" << logic[5] << "),\n";
216  myfile << "\t\t." << logic[2] << "_o(" << logic[2] << "),\n";
217  myfile << "\t\t." << logic[6] << "_i(" << logic[6] << "),\n";
218  myfile << "\t\t." << logic[3] << "_i(" << logic[3] << "),\n";
219  myfile << "\t\t." << logic[4] << "_i(" << logic[4] << "),\n";
220  myfile << "\t\t." << logic[10] << "_o(" << logic[10] << "),\n";
221  myfile << "\t\t." << logic[14] << "_o( " << logic[14] << "),\n";
222  myfile << "\t\t." << logic[11] << "_o( " << logic[11] << "),\n";
223  myfile << "\t\t." << logic[7] << "_o(" << logic[7] << "),\n";
224  myfile << "\t\t." << logic[12] << "_o(" << logic[12] << "),\n";
225  myfile << "\t\t." << logic[13] << "_i(" << logic[13] << "),\n";
226  myfile << "\t\t." << logic[8] << "_i( " << logic[8] << "),\n";
227  myfile << "\t\t." << logic[9] << "_i( " << logic[9] << "),\n";
228  myfile << "\t\t." << logic[17] << "_o( " << logic[17] << "),\n";
229  myfile << "\t\t.apu_master_req_o(),\n";
230  myfile << "\t\t.apu_master_ready_o(),\n";
231  myfile << "\t\t.apu_master_gnt_i(),\n";
232  myfile << "\t\t.apu_master_operands_o(),\n";
233  myfile << "\t\t.apu_master_op_o(),\n";
234  myfile << "\t\t.apu_master_type_o(),\n";
235  myfile << "\t\t.apu_master_flags_o(),\n";
236  myfile << "\t\t.apu_master_valid_i(),\n";
237  myfile << "\t\t.apu_master_result_i (),\n";
238  myfile << "\t\t.apu_master_flags_i(),\n";
239  myfile << "\t\t." << logic[23] << "_i(" << logic[23] << "),\n";
240  myfile << "\t\t." << logic[24] << "_i(" << logic[24] << "),\n";
241  myfile << "\t\t." << logic[25] << "_i(" << logic[25] << "),\n";
242  myfile << "\t\t." << logic[26] << "_i(" << logic[26] << "),\n";
243  myfile << "\t\t." << logic[27] << "_i(" << logic[27] << "),\n";
244  myfile << "\t\t." << logic[28] << "_i(" << logic[28] << "),\n";
245  myfile << "\t\t." << logic[20] << "_o(" << logic[20] << "),\n";
246  myfile << "\t\t." << logic[21] << "_o(" << logic[21] << "),\n";
247  myfile << "\t\t." << logic[22] << "_i(" << logic[22] << "),\n";
248  myfile << "\t\t." << logic[19] << "(" << logic[19] << "),\n";
249  myfile << "\t\t." << logic[18] << "(" << logic[18] << "),\n";
250  myfile << "\t\t." <<input[2] << "(" << input[2] << "),\n";
251  myfile << "\t\t." << logic[36] << "(" << logic[36] << "),\n";
252  myfile << "\t\t.ext_perf_counters_i(),\n";
253  myfile << "\t\t.fregfile_disable_i(1'b0));\n\n";
254 
255  myfile << "\talways @(posedge " << input[0] << " or negedge " << input[1] << ") begin\n";
256  myfile << "\t\tif (~" << input[1] << ") begin\n";
257  for (int i = 0; i < io_port.size(); i++) {
258  myfile <<"\t\t\t" << io_port[i][0] << " <= '0;\n";
259  }
260  myfile << "\t\t\t" << logic[1] << " <= '0;\n";
261  myfile << "\t\t\t" << logic[31] << " <= 1'b0;\n";
262  myfile << "\t\t\t" << logic[15] << " <= '0;\n";
263  myfile << "\t\t\t" << logic[38] << " <= '0;\n";
264  myfile << "\t\t\t" << logic[40] << " <= '0;\n";
265  myfile << "\t\t\t" << logic[42] << " <= '1;\n";
266  myfile << "\t\t\t" << logic[43] << " <= '0;\n";
267  myfile << "\t\tend else begin\n";
268  myfile << "\t\t\tif (data_req) begin\n";
269  myfile << "\t\t\t\tif (data_addr[" << mem_index+1 << "]) begin\n";
270  myfile << "\t\t\t\t\tif (data_we) begin\n";
271  for (int i = 0; i < io_port.size(); i++) {
272  myfile << "\t\t\t\t\t\t";
273  if(i == 0) {
274  myfile << "if ";
275  } else {
276  myfile << "end else if ";
277  }
278  myfile << "(data_addr[9:2] == " << i << ") begin\n";
279  myfile << "\t\t\t\t\t\t\t" << io_port[i][0] << " <= data_wdata;\n";
280  }
281  myfile << "\t\t\t\t\t\tend else if(data_addr[9:2] == " << io_port.size() << ") begin\n";
282  myfile << "\t\t\t\t\t\t\tcounter <= data_wdata;\n";
283  myfile << "\t\t\t\t\t\t\tCGRA_Enable <= 1'b1;\n";
284  myfile << "\t\t\t\t\t\t\tuse_counter <= 1'b1;\n";
285  myfile << "\t\t\t\t\t\tend else if(data_addr[9:2] == " << io_port.size() + 1 << ") begin\n";
286  myfile << "\t\t\t\t\t\t\tCGRA_Enable <= 1'b1;\n";
287  myfile << "\t\t\t\t\t\t\tuse_counter <= 1'b0;\n";
288  myfile << "\t\t\t\t\t\tend else if(data_addr[9:2] == " << io_port.size() + 2 << ") begin\n";
289  myfile << "\t\t\t\t\t\t\tCGRA_Reset_Control <= data_wdata;\n";
290  myfile << "\t\t\t\t\t\tend else if(data_addr[9:2] == " << io_port.size() + 3 << ") begin\n";
291  myfile << "\t\t\t\t\t\t\tselect_port <= data_wdata;\n";
292  myfile << "\t\t\t\t\t\tend\n";
293  myfile << "\t\t\t\t\tend else begin\n";
294  for (int i = 0; i < io_port.size(); i++) {
295  myfile << "\t\t\t\t\t\t";
296  if(i == 0) {
297  myfile << "if ";
298  } else {
299  myfile << "end else if ";
300  }
301  myfile << "(data_addr[9:2] == " << i << ") begin\n";
302  myfile << "\t\t\t\t\t\t\tdata_rdata_port <= " << io_port[i][1] << ";\n";
303  }
304  myfile << "\t\t\t\t\t\tend else if (data_addr[9:2] == " << io_port.size() << ") begin\n";
305  myfile << "\t\t\t\t\t\t\tif (counter <= 3) begin\n";
306  myfile << "\t\t\t\t\t\t\t\tdata_rdata_port <= 1;\n";
307  myfile << "\t\t\t\t\t\t\tend else begin\n";
308  myfile << "\t\t\t\t\t\t\t\tdata_rdata_port <= 0;\n";
309  myfile << "\t\t\t\t\t\t\tend\n";
310  myfile << "\t\t\t\t\t\tend else if (data_addr[9:2] == " << io_port.size() + 1 << ") begin\n";
311  myfile << "\t\t\t\t\t\t\tif (end_cgra == 1) begin\n";
312  myfile << "\t\t\t\t\t\t\t\tdata_rdata_port <= 1;\n";
313  myfile << "\t\t\t\t\t\t\tend else begin\n";
314  myfile << "\t\t\t\t\t\t\t\tdata_rdata_port <= 0;\n";
315  myfile << "\t\t\t\t\t\t\tend\n";
316  myfile << "\t\t\t\t\t\tend\n";
317  myfile << "\t\t\t\t\tend\n";
318  myfile << "\t\t\t\tend\n";
319  myfile << "\t\t\tend\n";
320  myfile << "\t\t\tif (use_counter) begin\n";
321  myfile << "\t\t\t\tif (CGRA_Enable) begin\n";
322  myfile << "\t\t\t\t\tif (counter == 0) begin\n";
323  myfile << "\t\t\t\t\t\tCGRA_Enable <= 1'b0;\n";
324  myfile << "\t\t\t\t\tend else begin\n";
325  myfile << "\t\t\t\t\t\tcounter <= counter - 1;\n";
326  myfile << "\t\t\t\t\tend\n";
327  myfile << "\t\t\t\tend\n";
328  myfile << "\t\t\tend else begin\n";
329  myfile << "\t\t\t\tif (CGRA_Enable) begin\n";
330  myfile << "\t\t\t\t\tif (end_port == 1) begin\n";
331  myfile << "\t\t\t\t\t\tCGRA_Enable <= 1'b0;\n";
332  myfile << "\t\t\t\t\t\tend_cgra <= 1'b1;\n";
333  myfile << "\t\t\t\t\tend\n";
334  myfile << "\t\t\t\tend\n";
335  myfile << "\t\t\tend\n";
336  myfile << "\t\tend\n";
337  myfile << "\tend\n\n";
338  myfile << "\talways_comb begin\n";
339  myfile << "\t\tif(" << logic[10] << " < 2 ** " << to_string(mem_index+1) << ") begin\n";
340  myfile << "\t\t\t" << logic[13] << " = " << logic[16] << ";\n";
341  myfile << "\t\tend else begin\n";
342  myfile << "\t\t\t" << logic[13] << " = " << logic[15] << ";\n\t\tend\n\tend\n\n";
343 
344  myfile << "\tcgra_U0 cgra_i(\n";
345  myfile << "\t\t." << logic[37] << "(" << logic[37] << "),\n";
346  myfile << "\t\t." << input[4] << "(" << input[4] << "),\n";
347  myfile << "\t\t." << logic[29] << "(" << logic[29] << "),\n";
348  myfile << "\t\t." << logic[30] << "(" << logic[30] << "),\n";
349  myfile << "\t\t.CGRA_Clock(" << input[0] << " & " << input[5] << "),\n";
350  myfile << "\t\t." << logic[31] << "(" << logic[31] << "),\n";
351  myfile << "\t\t." << input[6] << "(" << input[6] << " | " << logic[38] << "),\n";
352  for (int i = 0; i < io_port.size(); i++) {
353  myfile << "\t\t." << io_port[i][0] << "(" << io_port[i][0] << "),\n";
354  myfile << "\t\t." << io_port[i][1] << "(" << io_port[i][1] << "),\n";
355  }
356  for (int i = 0; i < mem_port.size(); i++) {
357  if (i == mem_port.size() - 1) {
358  myfile << "\t\t." << mem_port[i][0] << "(" << mem_port[i][0] << "),\n";
359  myfile << "\t\t." << mem_port[i][1] << "(" << mem_port[i][1] << "),\n";
360  myfile << "\t\t." << mem_port[i][2] << "(" << mem_port[i][2] << "),\n";
361  myfile << "\t\t." << mem_port[i][3] << "(" << mem_port[i][3] << ")\n";
362  } else {
363  myfile << "\t\t." << mem_port[i][0] << "(" << mem_port[i][0] << "),\n";
364  myfile << "\t\t." << mem_port[i][1] << "(" << mem_port[i][1] << "),\n";
365  myfile << "\t\t." << mem_port[i][2] << "(" << mem_port[i][2] << "),\n";
366  myfile << "\t\t." << mem_port[i][3] << "(" << mem_port[i][3] << "),\n";
367  }
368  }
369  myfile << "\t\t);\n\n";
370 
371  myfile << "\tCGRA_configurator configurator(\n";
372  myfile << "\t\t.clock(" << logic[37] << "),\n";
373  myfile << "\t\t.enable(" << input[8] << "),\n";
374  myfile << "\t\t.sync_reset(" << input[9] << "),\n";
375  myfile << "\t\t.bitstream(" << logic[29] << "),\n";
376  myfile << "\t\t.done(configurator_done));\n\n";
377  myfile << "\tmm_ram\n";
378  myfile << "\t\t#(.RAM_ADDR_WIDTH (" << mem_index+1 << "),\n";
379  myfile << "\t\t." << parameter[0] << " (" << parameter[0] << "))\n";
380  myfile << "\t\tram_i(\n";
381  myfile << "\t\t." << input[0] << "(" << input[0] << "),\n";
382  myfile << "\t\t." << input[1] << "(" << logic[0] << "),\n";
383  myfile << "\t\t." << input[6] << "(" << input[6] << " | " << logic[38] << "),\n";
384  myfile << "\t\t." << logic[2] << "_i(" << logic[2] << "),\n";
385  myfile << "\t\t." << logic[5] << "_i (" << logic[5] << "),\n";
386  myfile << "\t\t." << logic[6] << "_o(" << logic[6] << "),\n";
387  myfile << "\t\t." << logic[4] << "_o(" << logic[4] << "),\n";
388  myfile << "\t\t." << logic[3] << "_o(" << logic[3] << "),\n";
389  myfile << "\t\t.riscv_req_i(" << logic[7] << "),\n";
390  myfile << "\t\t.riscv_addr_i(" << logic[10] << "),\n";
391  myfile << "\t\t.riscv_we_i(" << logic[11] << "),\n";
392  myfile << "\t\t.riscv_be_i(" << logic[12] << " ),\n";
393  myfile << "\t\t.riscv_wdata_i(" << logic[14] << "),\n";
394  myfile << "\t\t.riscv_rdata_o( " << logic[13] << "_ram),\n";
395  myfile << "\t\t.riscv_rvalid_o ( " << logic[9] << "),\n";
396  myfile << "\t\t.riscv_gnt_o( " << logic[8] << "),\n";
397  myfile << "\t\t.cgra_enable( " << logic[31] << "),\n";
398  myfile << "\t\t." << logic[32] << " ( " << logic[32] << "),\n";
399  myfile << "\t\t." << logic[34] << "( " << logic[34] << "),\n";
400  myfile << "\t\t." << logic[33] << "( " << logic[33] << "),\n";
401  myfile << "\t\t." << logic[35] << "(" << logic[35] << "),\n";
402  myfile << "\t\t." << logic[21] << "_i( " << logic[21] << "),\n";
403  myfile << "\t\t." << logic[20] << "_i( " << logic[20] << " ),\n";
404  myfile << "\t\t." << logic[23] << "_o ( " << logic[23] << "),\n";
405  myfile << "\t\t." << logic[24] << "_o ( " << logic[24] << "),\n";
406  myfile << "\t\t." << logic[25] << "_o ( " << logic[25] << "),\n";
407  myfile << "\t\t." << logic[26] << "_o( " << logic[26] << " ),\n";
408  myfile << "\t\t." << logic[27] << "_o( " << logic[27] << " ),\n";
409  myfile << "\t\t." << logic[28] << "_o( " << logic[28] << "));\n";
410  myfile << "endmodule\n";
411 }
412 
413 void buildRam(ofstream &myfile, int mem_num, string *parameter, string *input, string *logic, int mem_size) {
414  myfile << "module mm_ram\n";
415  myfile << "\t#(parameter RAM_ADDR_WIDTH = 16,\n";
416  myfile << "\tparameter INSTR_RDATA_WIDTH = 128)\n";
417  myfile << "\t(input logic clk_i,\n";
418  myfile << "\tinput logic rst_ni,\n";
419  myfile << "\tinput logic CGRA_Reset,\n";
420  myfile << "\tinput logic instr_req_i,\n";
421  myfile << "\tinput logic [31:0] instr_addr_i,\n";
422  myfile << "\toutput logic [INSTR_RDATA_WIDTH-1:0] instr_rdata_o,\n";
423  myfile << "\toutput logic instr_rvalid_o,\n";
424  myfile << "\toutput logic instr_gnt_o,\n";
425  myfile << "\tinput logic riscv_req_i,\n";
426  myfile << "\tinput logic [31:0] riscv_addr_i,\n";
427  myfile << "\tinput logic riscv_we_i,\n";
428  myfile << "\tinput logic [3:0] riscv_be_i,\n";
429  myfile << "\tinput logic [31:0] riscv_wdata_i,\n";
430  myfile << "\toutput logic [31:0] riscv_rdata_o,\n";
431  myfile << "\toutput logic riscv_rvalid_o,\n";
432  myfile << "\toutput logic riscv_gnt_o,\n";
433  myfile << "\tinput logic cgra_enable,\n";
434  myfile << "\tinput logic [31:0] cgra_data_addr[" << mem_num - 1 << ":0],\n";
435  myfile << "\tinput logic [31:0] cgra_data_wdata[" << mem_num - 1 << ":0],\n";
436  myfile << "\toutput logic [" << 32 * mem_num - 1 << ":0] cgra_data_rdata,\n";
437  myfile << "\tinput logic [" << mem_num - 1 << ":0] cgra_we_i,\n";
438  myfile << "\tinput logic [4:0] irq_id_i,\n";
439  myfile << "\tinput logic irq_ack_i,\n";
440  myfile << "\toutput logic irq_software_o,\n";
441  myfile << "\toutput logic irq_timer_o,\n";
442  myfile << "\toutput logic irq_external_o,\n";
443  myfile << "\toutput logic [14:0] irq_fast_o,\n";
444  myfile << "\toutput logic irq_nmi_o,\n";
445  myfile << "\toutput logic [31:0] irq_fastx_o);\n";
446  myfile << "\tlocalparam int TIMER_IRQ_ID = 7;\n";
447  myfile << "\tlocalparam int INSTRUC_ADDR_WIDTH = 22;\n";
448  myfile << "\tlocalparam int BANK_ADDR_WIDTH = RAM_ADDR_WIDTH - " << (int)ceil(log2(mem_num)) << ";\n";
449  myfile << "\tenum logic [1:0]{RAM, MM, RND_STALL, ERR} select_rdata_d, select_rdata_q;\n";
450  myfile << "\tenum logic {T_RAM, T_PER} transaction;\n";
451  myfile << "\tenum logic [1:0] {IDLE, PERIPHEARL_VALID, WAIT_RAM_GNT, WAIT_RAM_VALID} state_valid_n, state_valid_q;\n";
452  myfile << "\tlogic [31:0] data_addr_aligned;\n";
453  myfile << "\tlogic data_rvalid_q;\n";
454  myfile << "\tlogic instr_rvalid_q;\n";
455  myfile << "\tlogic [INSTR_RDATA_WIDTH-1:0] core_instr_rdata;\n";
456  myfile << "\tlogic [31:0] core_data_rdata;\n";
457  myfile << "\tlogic [" << mem_num - 1 << ":0] ram_bank_enable;\n";
458  myfile << "\tlogic [RAM_ADDR_WIDTH-1:0] ram_data_addr;\n";
459  myfile << "\tlogic [31:0] ram_data_wdata;\n";
460  myfile << "\tlogic [31:0] ram_data_rdata;\n";
461  myfile << "\tlogic ram_data_we;\n";
462  myfile << "\tlogic [3:0] ram_data_be;\n";
463  myfile << "\tlogic ram_data_gnt;\n";
464  myfile << "\tlogic ram_data_valid;\n";
465  myfile << "\tlogic data_req_dec;\n";
466  myfile << "\tlogic [31:0] data_wdata_dec;\n";
467  myfile << "\tlogic [RAM_ADDR_WIDTH-1:0] data_addr_dec;\n";
468  myfile << "\tlogic data_we_dec;\n";
469  myfile << "\tlogic [3:0] data_be_dec;\n";
470  myfile << "\tlogic [RAM_ADDR_WIDTH-1:0] data_addr_dec_q;\n";
471  myfile << "\tlogic [INSTR_RDATA_WIDTH-1:0] ram_instr_rdata;\n";
472  myfile << "\tlogic ram_instr_req;\n";
473  myfile << "\tlogic [INSTRUC_ADDR_WIDTH-1:0] ram_instr_addr;\n";
474  myfile << "\tlogic ram_instr_gnt;\n";
475  myfile << "\tlogic ram_instr_valid;\n";
476  myfile << "\tlogic [31:0] timer_irq_mask_q;\n";
477  myfile << "\tlogic [31:0] timer_cnt_q;\n";
478  myfile << "\tlogic irq_timer_q;\n";
479  myfile << "\tlogic timer_reg_valid;\n";
480  myfile << "\tlogic timer_val_valid;\n";
481  myfile << "\tlogic [31:0] timer_wdata;\n";
482  myfile << "\tlogic [31:0] ram_data_rdata_tmp[0:3];\n";
483  myfile << "\tlogic [" << mem_num - 1 << ":0] cgra_bank_enable;\n";
484  myfile << "\ttypedef struct packed {\n";
485  myfile << "\t\tlogic irq_software;\n";
486  myfile << "\t\tlogic irq_timer;\n";
487  myfile << "\t\tlogic irq_external;\n";
488  myfile << "\t\tlogic [14:0] irq_fast;\n";
489  myfile << "\t\tlogic irq_nmi;\n";
490  myfile << "\t\tlogic [31:0] irq_fastx;\n";
491  myfile << "\t} Interrupts_tb_t;\n";
492  myfile << "\tInterrupts_tb_t irq_rnd_lines;\n";
493  myfile << "\talways_comb data_addr_aligned = {riscv_addr_i[31:2], 2'b0} ;\n";
494  myfile << "\talways_comb begin\n";
495  myfile << "\t\tdata_req_dec = '0;\n";
496  myfile << "\t\tdata_addr_dec = '0;\n";
497  myfile << "\t\tdata_wdata_dec = '0;\n";
498  myfile << "\t\tdata_we_dec = '0;\n";
499  myfile << "\t\tdata_be_dec = '0;\n";
500  myfile << "\t\ttimer_wdata = '0;\n";
501  myfile << "\t\ttimer_reg_valid = '0;\n";
502  myfile << "\t\ttimer_val_valid = '0;\n";
503  myfile << "\t\tselect_rdata_d = RAM;\n";
504  myfile << "\t\ttransaction = T_PER;\n";
505  myfile << "\t\tif (riscv_req_i) begin\n";
506  myfile << "\t\t\tif (riscv_we_i) begin\n";
507  myfile << "\t\t\t\tif (riscv_addr_i < 2 ** RAM_ADDR_WIDTH) begin\n";
508  myfile << "\t\t\t\t\tdata_req_dec = riscv_req_i;\n";
509  myfile << "\t\t\t\t\tdata_addr_dec = riscv_addr_i[RAM_ADDR_WIDTH-1:0];\n";
510  myfile << "\t\t\t\t\tdata_wdata_dec = riscv_wdata_i;\n";
511  myfile << "\t\t\t\t\tdata_we_dec = riscv_we_i;\n";
512  myfile << "\t\t\t\t\tdata_be_dec = riscv_be_i;\n";
513  myfile << "\t\t\t\t\ttransaction = T_RAM;\n";
514  myfile << "\t\t\t\tend else begin\n";
515  myfile << "\t\t\t\t\tdata_req_dec = 0;\n";
516  myfile << "\t\t\t\t\tif (riscv_addr_i == 32'h1500_0000) begin\n";
517  myfile << "\t\t\t\t\t\ttimer_wdata = riscv_wdata_i;\n";
518  myfile << "\t\t\t\t\t\ttimer_reg_valid = '1;\n";
519  myfile << "\t\t\t\t\tend else if (riscv_addr_i == 32'h1500_0004) begin\n";
520  myfile << "\t\t\t\t\t\ttimer_wdata = riscv_wdata_i;\n";
521  myfile << "\t\t\t\t\t\ttimer_val_valid = '1;\n";
522  myfile << "\t\t\t\t\tend\n";
523  myfile << "\t\t\t\tend\n";
524  myfile << "\t\t\tend else begin\n";
525  myfile << "\t\t\t\tif (riscv_addr_i < 2 ** RAM_ADDR_WIDTH) begin\n";
526  myfile << "\t\t\t\t\tselect_rdata_d = RAM;\n";
527  myfile << "\t\t\t\t\tdata_req_dec = riscv_req_i;\n";
528  myfile << "\t\t\t\t\tdata_addr_dec = riscv_addr_i[RAM_ADDR_WIDTH-1:0];\n";
529  myfile << "\t\t\t\t\tdata_wdata_dec = riscv_wdata_i;\n";
530  myfile << "\t\t\t\t\tdata_we_dec = riscv_we_i;\n";
531  myfile << "\t\t\t\t\tdata_be_dec = riscv_be_i;\n";
532  myfile << "\t\t\t\t\ttransaction = T_RAM;\n";
533  myfile << "\t\t\t\tend else\n";
534  myfile << "\t\t\t\t\tselect_rdata_d = ERR;\n";
535  myfile << "\t\t\tend\n";
536  myfile << "\t\tend\n";
537  myfile << "\tend\n";
538  myfile << "\talways_comb begin: read_mux\n";
539  myfile << "\t\triscv_rdata_o = '0;\n";
540  myfile << "\t\tif(select_rdata_q == RAM) begin\n";
541  myfile << "\t\t\triscv_rdata_o = core_data_rdata;\n";
542  myfile << "\t\tend\n";
543  myfile << "\tend\n";
544  myfile << "\talways_ff @(posedge clk_i, negedge rst_ni) begin: tb_timer\n";
545  myfile << "\t\tif(~rst_ni) begin\n";
546  myfile << "\t\t\ttimer_irq_mask_q <= '0;\n";
547  myfile << "\t\t\ttimer_cnt_q <= '0;\n";
548  myfile << "\t\t\tirq_timer_q <= '0;\n";
549  myfile << "\t\tend else begin\n";
550  myfile << "\t\t\tif(timer_reg_valid) begin\n";
551  myfile << "\t\t\t\ttimer_irq_mask_q <= timer_wdata;\n";
552  myfile << "\t\t\tend else if(timer_val_valid) begin\n";
553  myfile << "\t\t\t\ttimer_cnt_q <= timer_wdata;\n";
554  myfile << "\t\t\tend else begin\n";
555  myfile << "\t\t\t\tif(timer_cnt_q > 0)\n";
556  myfile << "\t\t\t\t\ttimer_cnt_q <= timer_cnt_q - 1;\n";
557  myfile << "\t\t\t\tif(timer_cnt_q == 1)\n";
558  myfile << "\t\t\t\t\tirq_timer_q <= 1'b1 && timer_irq_mask_q[TIMER_IRQ_ID];\n";
559  myfile << "\t\t\t\tif(irq_ack_i == 1'b1 && irq_id_i == TIMER_IRQ_ID)\n";
560  myfile << "\t\t\t\t\tirq_timer_q <= '0;\n";
561  myfile << "\t\t\tend\n";
562  myfile << "\t\tend\n";
563  myfile << "\tend\n";
564  for (int i = 0; i < mem_num; i++) {
565  myfile << "\tdp_ram\n";
566  myfile << "\t\t#(.ADDR_WIDTH (RAM_ADDR_WIDTH), .BANK_ADDR_WIDTH(BANK_ADDR_WIDTH))\n";
567  myfile << "\tdp_ram_" << i << "\n";
568  myfile << "\t\t(\n";
569  myfile << "\t\t.clk_i ( clk_i ),\n";
570  myfile << "\t\t.rst_ni ( rst_ni ),\n";
571  myfile << "\t\t.rst_CGRA ( CGRA_Reset ),\n";
572  myfile << "\t\t.en_a_i ( cgra_bank_enable[" << i << "] ),\n";
573  myfile << "\t\t.addr_a_i ( cgra_data_addr[" << i << "][RAM_ADDR_WIDTH-1:0] ),\n";
574  myfile << "\t\t.wdata_a_i ( cgra_data_wdata[" << i << "] ),\n";
575  myfile << "\t\t.rdata_a_o ( cgra_data_rdata[" << i*32+31 << ":" << i*32 << "] ),\n";
576  myfile << "\t\t.we_a_i ( cgra_we_i[" << i << "] ),\n";
577  myfile << "\t\t.be_a_i ( 4'b1111 ),\n";
578  myfile << "\t\t.en_b_i ( ram_bank_enable[" << i << "] ),\n";
579  myfile << "\t\t.addr_b_i ( ram_data_addr ),\n";
580  myfile << "\t\t.wdata_b_i ( ram_data_wdata ),\n";
581  myfile << "\t\t.rdata_b_o ( ram_data_rdata_tmp[" << i << "] ),\n";
582  myfile << "\t\t.we_b_i ( ram_data_we ),\n";
583  myfile << "\t\t.be_b_i ( ram_data_be ));\n";
584  }
585 
586  myfile << "\tinstruc_ram\n";
587  myfile << "\t\t#(.ADDR_WIDTH (INSTRUC_ADDR_WIDTH),\n";
588  myfile << "\t\t.INSTR_RDATA_WIDTH(INSTR_RDATA_WIDTH))\n";
589  myfile << "\tinstruc_ram_i\n";
590  myfile << "\t\t(.clk_i( clk_i ),\n";
591  myfile << "\t\t.en_a_i( ram_instr_req ),\n";
592  myfile << "\t\t.addr_a_i( ram_instr_addr ),\n";
593  myfile << "\t\t.rdata_a_o( ram_instr_rdata )\n";
594  myfile << "\t\t);\n";
595 
596  myfile << "\talways_ff @(posedge clk_i, negedge rst_ni) begin\n";
597  myfile << "\t\tif (~rst_ni) begin\n";
598  myfile << "\t\t\tselect_rdata_q <= RAM;\n";
599  myfile << "\t\t\tdata_rvalid_q <= '0;\n";
600  myfile << "\t\t\tinstr_rvalid_q <= '0;\n";
601  myfile << "\t\t\tstate_valid_q <= IDLE;\n";
602  myfile << "\t\t\tdata_addr_dec_q <= '0;\n";
603  myfile << "\t\tend else begin\n";
604  myfile << "\t\t\tselect_rdata_q <= select_rdata_d;\n";
605  myfile << "\t\t\tdata_rvalid_q <= data_req_dec;\n";
606  myfile << "\t\t\tinstr_rvalid_q <= ram_instr_req;\n";
607  myfile << "\t\t\tstate_valid_q <= state_valid_n;\n";
608  myfile << "\t\t\tdata_addr_dec_q <= data_addr_dec;\n";
609  myfile << "\t\tend\n";
610  myfile << "\tend\n";
611  myfile << "\talways_comb begin\n";
612  myfile << "\t\triscv_gnt_o = 1'b0;\n";
613  myfile << "\t\triscv_rvalid_o = 1'b0;\n";
614  myfile << "\t\tstate_valid_n = state_valid_q;\n";
615  myfile << "\t\tunique case(state_valid_q)\n";
616  myfile << "\t\t\tIDLE:\n";
617  myfile << "\t\t\tbegin\n";
618  myfile << "\t\t\t\tif(riscv_req_i) begin\n";
619  myfile << "\t\t\t\t\tif(transaction == T_RAM) begin\n";
620  myfile << "\t\t\t\t\t\triscv_gnt_o = ram_data_gnt;\n";
621  myfile << "\t\t\t\t\t\tif(ram_data_gnt) begin\n";
622  myfile << "\t\t\t\t\t\t\tstate_valid_n = WAIT_RAM_VALID;\n";
623  myfile << "\t\t\t\t\t\tend else begin\n";
624  myfile << "\t\t\t\t\t\t\tstate_valid_n = WAIT_RAM_GNT;\n";
625  myfile << "\t\t\t\t\t\tend\n";
626  myfile << "\t\t\t\t\tend else begin\n";
627  myfile << "\t\t\t\t\t\tstate_valid_n = PERIPHEARL_VALID;\n";
628  myfile << "\t\t\t\t\t\triscv_gnt_o = 1'b1;\n";
629  myfile << "\t\t\t\t\tend\n";
630  myfile << "\t\t\t\tend\n";
631  myfile << "\t\t\tend\n";
632  myfile << "\t\t\tPERIPHEARL_VALID:\n";
633  myfile << "\t\t\tbegin\n";
634  myfile << "\t\t\t\triscv_rvalid_o = 1'b1;\n";
635  myfile << "\t\t\t\tif(riscv_req_i) begin\n";
636  myfile << "\t\t\t\t\tif(transaction == T_RAM) begin\n";
637  myfile << "\t\t\t\t\t\triscv_gnt_o = ram_data_gnt;\n";
638  myfile << "\t\t\t\t\t\tif(ram_data_gnt) begin\n";
639  myfile << "\t\t\t\t\t\t\tstate_valid_n = WAIT_RAM_VALID;\n";
640  myfile << "\t\t\t\t\t\tend else begin\n";
641  myfile << "\t\t\t\t\t\t\tstate_valid_n = WAIT_RAM_GNT;\n";
642  myfile << "\t\t\t\t\t\tend\n";
643  myfile << "\t\t\t\t\tend else begin\n";
644  myfile << "\t\t\t\t\t\tstate_valid_n = PERIPHEARL_VALID;\n";
645  myfile << "\t\t\t\t\t\triscv_gnt_o = 1'b1;\n";
646  myfile << "\t\t\t\t\tend\n";
647  myfile << "\t\t\t\tend else state_valid_n = IDLE;\n";
648  myfile << "\t\t\tend\n";
649  myfile << "\t\t\tWAIT_RAM_GNT:\n";
650  myfile << "\t\t\tbegin\n";
651  myfile << "\t\t\t\triscv_rvalid_o = 1'b0;\n";
652  myfile << "\t\t\t\tif(riscv_req_i) begin\n";
653  myfile << "\t\t\t\t\triscv_gnt_o = ram_data_gnt;\n";
654  myfile << "\t\t\t\t\tif(ram_data_gnt) begin\n";
655  myfile << "\t\t\t\t\t\tstate_valid_n = WAIT_RAM_VALID;\n";
656  myfile << "\t\t\t\t\tend else begin\n";
657  myfile << "\t\t\t\t\t\tstate_valid_n = WAIT_RAM_GNT;\n";
658  myfile << "\t\t\t\t\tend\n";
659  myfile << "\t\t\t\tend else state_valid_n = IDLE;\n";
660  myfile << "\t\t\tend\n";
661  myfile << "\t\t\tWAIT_RAM_VALID:\n";
662  myfile << "\t\t\tbegin\n";
663  myfile << "\t\t\t\triscv_rvalid_o = ram_data_valid;\n";
664  myfile << "\t\t\t\tif(ram_data_valid) begin\n";
665  myfile << "\t\t\t\t\tif(riscv_req_i) begin\n";
666  myfile << "\t\t\t\t\t\tif(transaction == RAM) begin\n";
667  myfile << "\t\t\t\t\t\t\triscv_gnt_o = ram_data_gnt;\n";
668  myfile << "\t\t\t\t\t\t\tif(ram_data_gnt) begin\n";
669  myfile << "\t\t\t\t\t\t\t\tstate_valid_n = WAIT_RAM_VALID;\n";
670  myfile << "\t\t\t\t\t\t\tend else begin\n";
671  myfile << "\t\t\t\t\t\t\t\tstate_valid_n = WAIT_RAM_GNT;\n";
672  myfile << "\t\t\t\t\t\t\tend\n";
673  myfile << "\t\t\t\t\t\tend else begin\n";
674  myfile << "\t\t\t\t\t\t\tstate_valid_n = PERIPHEARL_VALID;\n";
675  myfile << "\t\t\t\t\t\t\triscv_gnt_o = 1'b1;\n";
676  myfile << "\t\t\t\t\t\tend\n";
677  myfile << "\t\t\t\t\tend else state_valid_n = IDLE;\n";
678  myfile << "\t\t\t\tend\n";
679  myfile << "\t\t\tend\n";
680  myfile << "\t\t\tdefault: begin\n";
681  myfile << "\t\t\tend\n";
682  myfile << "\t\tendcase\n";
683  myfile << "\tend\n";
684 
685  myfile << "\tassign instr_gnt_o = ram_instr_gnt;\n";
686  myfile << "\tassign instr_rvalid_o = ram_instr_valid;\n";
687  myfile << "\tassign instr_rdata_o = core_instr_rdata;\n";
688  myfile << "\talways_comb begin\n";
689  myfile << "\t\tram_instr_req = instr_req_i;\n";
690  myfile << "\t\tram_instr_addr = instr_addr_i;\n";
691  myfile << "\t\tram_instr_gnt = instr_req_i;\n";
692  myfile << "\t\tram_instr_valid = instr_rvalid_q;\n";
693  myfile << "\t\tcore_instr_rdata = ram_instr_rdata;\n";
694  myfile << "\t\tram_data_valid = data_rvalid_q;\n";
695  myfile << "\t\tram_data_gnt = data_req_dec;\n";
696  myfile << "\t\tcore_data_rdata = ram_data_rdata;\n";
697  myfile << "\t\tram_data_wdata = data_wdata_dec;\n";
698  myfile << "\t\tram_data_we = data_we_dec;\n";
699  myfile << "\t\tram_data_be = data_be_dec;\n";
700  myfile << "\t\tram_data_addr = data_addr_dec[BANK_ADDR_WIDTH - 1:0];\n";
701  myfile << "\t\tcgra_bank_enable = {" << mem_num << "{cgra_enable}};\n";
702  myfile << "\tend\n";
703  myfile << "\talways_comb begin\n";
704  myfile << "\t\tram_bank_enable = '0;\n";
705  for (int i = 0 ; i < mem_num; i++) {
706  myfile << "\t\t";
707  if(i == 0) {
708  myfile << "if (data_addr_dec < 2**BANK_ADDR_WIDTH) begin";
709  } else {
710  myfile << "end else if (data_addr_dec > 2**BANK_ADDR_WIDTH * " <<
711  i << " - 1 && data_addr_dec < 2**BANK_ADDR_WIDTH * " << i+1 << ") begin;\n";
712  }
713  myfile << "\t\t\tram_bank_enable[" << i << "] = data_req_dec;\n";
714  }
715  myfile << "\t\tend\n";
716  myfile << "\tend\n";
717  myfile << "\talways_comb begin\n";
718  myfile << "\t\tram_data_rdata = '0;\n";
719  for (int i = 0 ; i < mem_num; i++) {
720  myfile << "\t\t";
721  if(i == 0) {
722  myfile << "if (data_addr_dec_q < 2**BANK_ADDR_WIDTH) begin";
723  } else {
724  myfile << "end else if (data_addr_dec_q > 2**BANK_ADDR_WIDTH * " <<
725  i << " - 1 && data_addr_dec_q < 2**BANK_ADDR_WIDTH * " << i+1 << ") begin;\n";
726  }
727  myfile << "\t\t\tram_data_rdata = ram_data_rdata_tmp[" << i << "];\n";
728  }
729  myfile << "\t\tend\n";
730  myfile << "\tend\n";
731  myfile << "\tassign irq_software_o = irq_rnd_lines.irq_software;\n";
732  myfile << "\tassign irq_timer_o = irq_rnd_lines.irq_timer | irq_timer_q;\n";
733  myfile << "\tassign irq_external_o = irq_rnd_lines.irq_external;\n";
734  myfile << "\tassign irq_fast_o = irq_rnd_lines.irq_fast;\n";
735  myfile << "\tassign irq_nmi_o = irq_rnd_lines.irq_nmi;\n";
736  myfile << "\tassign irq_fastx_o = irq_rnd_lines.irq_fastx;\n";
737  myfile << "endmodule";
738 }
739 
740 bool IsPowerOfTwo(int x)
741 {
742  return (x != 0) && ((x & (x - 1)) == 0);
743 }
744 
745 void buildHybridHeader(ofstream &header, vector<string> memPort, vector<string> ioPort) {
746  int io = 4194304;
747  for (int i = 0; i < ioPort.size(); i++) {
748  header << "\t.set " << ioPort[i] << ", " << io + 4*i << std::endl;
749  }
750  header << "\t.set counter " << ", " << io + 4*ioPort.size() << std::endl;
751  header << "\t.set endport" << ", " << io + 4*(ioPort.size()+1) << std::endl;
752  header << "\t.set reset" << ", " << io + 4*(ioPort.size()+2) << std::endl;
753  header << "\t.set selport" << ", " << io + 4*(ioPort.size()+3) << std::endl;
754  for (int i = 0; i < memPort.size(); i++) {
755  header << "\t.set " << memPort[i] << ", " << io/memPort.size()*i << std::endl;
756  }
757 }
buildRam
void buildRam(ofstream &myfile, int mem_num, string *parameter, string *input, string *logic, int mem_size)
Definition: Control.cpp:413
IsPowerOfTwo
bool IsPowerOfTwo(int x)
Definition: Control.cpp:740
to_string
const std::string & to_string(const OpGraphOpCode &opcode)
Definition: OpGraph.cpp:111
buildHybridHeader
void buildHybridHeader(ofstream &header, vector< string > memPort, vector< string > ioPort)
Definition: Control.cpp:745
buildControl
void buildControl(ofstream &myfile, vector< vector< string >> io_port, vector< vector< string >> mem_port, string *parameter, string *input, string *logic, int mem_index)
Definition: Control.cpp:96
buildComp
void buildComp(ofstream &myfile, std::vector< std::string > ports, int mem_size)
Definition: Control.cpp:10
Control.h
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