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CGRA-ME
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This is the complete list of members for IO, including all inherited members.
| addConfig(ConfigCell *c, std::vector< std::string > ConnectTo) | Module | |
| addConfig(std::string name, std::vector< std::string > ConnectTo, int contexts, bool isElastic) | Module | |
| addConnection(std::string src, std::string dst, bool isInMRRG=true) | Module | |
| addElasticConnection(std::string src, std::string dst) | Module | |
| addElasticPort(std::string portname, port_type pt, unsigned size) | Module | |
| addElasticPort(std::string portname, port_type pt, std::string ParameterName, unsigned size) | Module | |
| addParameter(std::string parameterName, unsigned parameterValue) | Module | |
| addPort(std::string portname, port_type pt, unsigned size) | Module | |
| addPort(std::string portname, port_type pt, unsigned size, bool isElastic) | Module | |
| addPort(std::string portname, port_type pt, std::string ParameterName, unsigned size) | Module | |
| addPort(std::string portname, port_type pt, std::string ParameterName, unsigned size, bool isElastic) | Module | |
| adds_synchronous_circuitry | Module | protected |
| addsSynchronousCircuitry() const | Module | inline |
| addSubModule(Module *m) | Module | |
| addSubModule(Module *m, double xPos, double yPos, double width, double height) | Module | |
| addVerilogPort(std::string name, port_type pt, std::string parameter, unsigned size) | Module | |
| area | Module | |
| configcells | Module | |
| connections | Module | |
| connectPorts(std::string src, std::string dst, bool isElastic) | Module | |
| CoreIRGenFunctionality() | Module | protectedvirtual |
| CoreIRGenModuleVerilog(CoreIR::Context *c, int contexts) | Module | virtual |
| CoreIRGetModulesToPrint(std::queue< Module * > &ToPrint, std::set< std::string > &PrintedModMap) | Module | protected |
| createMRRG(unsigned contexts) | Module | virtual |
| data_size | Module | protected |
| DetermineConnections(StringMatrix &Matrix, PrintList &WireList, PrintList &SubmodList, PrintList &AssignList) | Module | protected |
| FindPortIndex(std::string PortName) | Module | protected |
| FindSubmoduleIndex(std::string SubmoduleName) | Module | protected |
| genConfigOrder(std::vector< ConfigCell * > &ConfigTable) const | Module | |
| GenConnections() | Module | protectedvirtual |
| GenerateMatrix(StringMatrix &Matrix) | Module | protected |
| GenericName() override | IO | virtual |
| GenFunctionality() | Module | protectedvirtual |
| GenModuleHeader(bool HasConfig, bool HasRegisters) | Module | protected |
| GenModuleVerilog() | Module | virtual |
| GenParameters() | Module | protected |
| GenPortSpecs(bool HasConfig, bool HasRegisters) | Module | protected |
| genVerilogCGRAME(std::string dir) | Module | |
| genVerilogCoreIR(std::string dir, int contexts) | Module | |
| getBitConfig(const MRRG &mrrg, const OpGraph &og, const Mapping &map, const ConfigCell &ccell, const MRRGNodesFromOpNode &mrrg_nodes_from_op_node, const MRRGNodesFromValNode &mrrg_nodes_from_val_node) const | Module | inlinevirtual |
| GetConfigsToPrint(std::queue< ConfigCell * > &q, std::set< unsigned > &uniq) | Module | protected |
| getModule(std::string, std::string err_context="") | Module | |
| getModuleFromPortName(std::string full_port_name, std::string err_context="") | Module | |
| GetModulesToPrint(std::queue< Module * > &ToPrint, std::set< std::string > &PrintedModMap) | Module | |
| getName() const | Module | inline |
| getNodePosition(const std::string &nodeName) | Module | |
| getPort(std::string full_port_name, std::string err_context="") | Module | |
| getSize() const | Module | inline |
| getSubModule(std::string) | Module | |
| getSubModulePosition(const std::string &submodName) | Module | |
| getTriState() | IO | |
| hasConfigCells() const | Module | inline |
| hierarchyLevel | Module | |
| IO(std::string, Location, unsigned size=DEFAULT_SIZE, int contexts=1, bool isElastic=false) | IO | |
| isElastic | Module | |
| isLastInHierarchy | Module | |
| isSubModule(Module *) | Module | |
| loc | Module | |
| makeCoreIRInterfaceGenerator() | Module | |
| makeCoreIRModuleDefinitonGenerator() | Module | |
| Module(std::string name, Location, unsigned size=DEFAULT_SIZE, bool isElastic=false) | Module | |
| Module(std::string name, std::string template_name, Location loc={0, 0}, unsigned size=DEFAULT_SIZE, bool isElastic=false) | Module | |
| Module(const Module &)=delete | Module | |
| Module(Module &&)=default | Module | |
| name | Module | protected |
| node_relative_position | Module | protected |
| operator=(const Module &)=delete | Module | |
| operator=(Module &&)=default | Module | |
| overridenFanoutCount | Module | |
| parameterlist | Module | |
| parent | Module | |
| ports | Module | |
| portsToPropagate | Module | |
| print() | Module | |
| print_configcells() | Module | |
| print_connections() | Module | |
| print_dot() | Module | |
| print_ports() | Module | |
| print_submodules() | Module | |
| ResolveVerilogParameters() const | Module | protectedvirtual |
| ReturnPath() const | Module | inline |
| setNodePosition(const std::string &nodeName, double x, double y) | Module | |
| submodsSet | Module | |
| submodule_relative_position | Module | protected |
| submodules | Module | |
| templateName | Module | protected |
| ~IO() | IO | virtual |
| ~Module() | Module | virtual |
1.8.17